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*Read Me/FAQ/General Info...
**Intro:...
**Quote style:...
**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
**IBM PC/XT/AT...
*ACC Micro...
**Notes:...
**ACC82010 AT Chip Set (286 12.5/16MHz Max) c88...
**ACC82020 Turbo PC/AT Chip Set (286/386SX 25MHz Max) c88...
**ACC82021 Turbo PC/AT Chip Set (286/386SX 25MHz Max) >88...
**ACC82300 386 AT Chip Set (386DX) c88...
**ACC82C100 Single-Chip PC/XT Systems-Controller c90...
**ACC83000 Model 30 Integrated Chip Set (MCA) c88...
**ACC85000/A Model 50/60 Chipset (MCA) c88...
**ACC1000 Turbo PC/XT Integrated Bus and Peripheral Ctrl. 04/02/88...
**ACC2036 Single Chip Solution 2036 (286/386SX) <Jul92
***Info:...
***Configurations:...
***Features:...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT <Jul92...
***Info:...
***Configurations:...
***Features:...
**ACC2048 WB 486 Notebook/Embedded Single Chip [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96...
***Info:...
***Configurations:...
***Features:...
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
***Notes:...
***Configurations:...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
***Notes:...
***Info:...
***Configurations:...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
***Info:...
***Configurations:...
***Features:...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2268 ?486 [no datasheet] ?...
***Configurations:...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
***Notes:...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96...
***Info:...
***Versions:...
***Features:...
**ACC2020 Power Management Chip c92...
***info:...
***Versions:...
***Features:...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
***Info:...
***Versions:...
***Features:...
**
**Other chips...
*ALD...
**Notes:...
**Chips with no datasheet:...
**93C488 5x86/486 Single Chip PCI controller <Aug96...
***Info:...
***Configurations:...
***Features:...
*ALi...
**Notes:...
**M1207 286 Single Chip [no datasheet] ?...
***Notes:...
**M1217/M1209 386SX/SLC Single Chip (40MHz) [no datasheet] c91...
***Notes:...
**M1219 386DX/486 ISA Cache? Single Chip [no datasheet] ?
**M1419 386DX/486 ISA Cache Single Chip [no datasheet] c91
**Ml429/31/35 486 VLB/PCI/ISA [no datasheet, some info] cOct93...
***Notes:...
***Configurations:...
**M1439/31/45 486 VLB/PCI/ISA [no datasheet, some info] <May95...
***Notes:...
***Configurations:...
**M1489/87 FinALi-486 PCI Chipset <Feb95...
***Info:...
***Configurations:...
***Features:...
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
***Notes:...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
***Configurations:...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
***Notes:...
***Configurations:...
**M1521/23 Aladdin III 50-66MHz <Nov96...
***Info:...
****M1521 System Controller:...
****M1523 PCI-to-ISA Bridge:...
***Configurations:...
***Features:...
****M1521 System Controller:...
****M1523 PCI-to-ISA Bridge:...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
***Info:...
****M1531 CPU-to-PCI bridge, Memory, Cache and Buffer Controller:...
****M1533 PCI-to-ISA Bus Bridge:...
***Configurations:...
***Features:...
****M1531 CPU-to-PCI bridge, Memory, Cache and Buffer Controller:...
****M1533 PCI-to-ISA Bus Bridge:...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
***Info:...
****M1541/1542 AGP/CPU-to-PCI bridge/Memory/Cache and Buffer Ctrl.:...
****M1543/C PCI-to-ISA Bus Bridge with Super I/O & Fast IR:...
***Configurations:...
***Features:...
****M1541/1542 AGP/CPU-to-PCI bridge/Memory/Cache and Buffer Ctrl.:...
****M1543/C PCI-to-ISA Bus Bridge with Super I/O & Fast IR:...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
***Notes:...
***Info & Features:...
***Configurations:...
**M6117 386SX Single Chip PC <97...
***Notes:...
***Info:...
***Versions:...
***Features:...
**
**Support Chips:
**M1535/D South Bridge ?...
***Info:...
***Versions:...
***Features:...
**
**May not exist:...
**Later Chipsets:...
***PII...
***Athlon...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
**AMD Am286ZX/LX (286 Embeded CPU + integrated peripherals) ?
**AMD Elan Series (386/486 Embeded CPU + integrated peripherals) ?
**AMD 640/645 (Pentium Based on VIA VT82C590) [some info] c97...
**Later Chipsets:...
*Chips & Technologies...
**CS8220 PC/AT compatible CHIPSet (82C201/C202/A203/A204/A205)cOct85...
***Notes:...
***Info:...
****General:...
****82C201 (8Mhz) or 82C201-10 (10Mhz):...
****82C202: ...
****82A203:...
****82A204:...
****82A205:...
***Configurations:...
***Features;...
**CS8221 NEW Enhanced AT (NEAT) (82C211/82C212/82C215/82C206) c86...
***Info:...
***Configurations:...
***Features:...
**CS8223 LeAPset [no datasheet] ?
**CS8225 CHIPS/250 PS/2 50/60 [no datasheet, some info] c88...
**CS8227 CHIPSlite (82C235/82C641) ?...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86...
***Info:...
***Configurations:...
***Features:...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
***Notes:...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
***Info:...
***Configurations:...
***Features:...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
***Notes:...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
***Notes:...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
***Info:...
***Configurations:...
***Features:...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
***Info:...
***Configurations:...
***Features:...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
***Info:...
***Configurations:...
***Features:...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
***Info:...
***Configurations:...
***Features:...
**CS8285 PEAKsx (82C836/82C835) c91...
***Info:...
***Configurations:...
***Features:...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
***Notes:...
***Configurations:...
**CS4000 WinCHIPS (64200/84021/84025) c92...
***Info:...
***Configurations:...
***Features:...
**CS4021 ISA/486 (84021/84025) c92...
***Info: ...
***Configurations:...
***Features:...
**CS4031 CHIPSet (84031/84035) 5/10/93...
***Info:...
***Configurations:...
***Features:...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
***Info:...
***Configurations:...
***Features:...
**CB8291 ELEAT [no datasheet] c90...
***Notes:...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
***Info:...
***Configurations:...
***Features:...
**82C110 IBM PS/2 Model 30/Super XT ?...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C235 Single Chip AT (SCAT) c89...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C836 Single Chip 386sx (SCATsx) <91...
***Info:...
***Configurations:...
***Features:...
**F8680/A PC/CHIP Single-Chip PC c93...
***Notes:...
***Info:...
***Configurations:...
***Features...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
***Info:...
****General:
The concept behind the 64200 'Windows Engine' (Wingine) is the
implementation of video display memory as a bank (or banks) of system
memory. The idea is that the system CPU (typically at least a
386-class processor) can manipulate pixels on the screen quickly if
the display memory bottleneck is removed. The video memory is
accessed directly by the system CPU as a frame buffer through the VRAM
random access port while the display is continuously being refreshed
via the VRAM serial data port.
Wingine is basically a standard 16-bit VGA with extensions. The
primary extension is to allow the system to directly access VRAM
display memory as system memory. Wingine operates in two modes:
'Windows Acceleration' mode and 'VGA' mode. In 'VGA' mode, Wingine
drives the video memory. Wingine uses the VRAMs as DRAMs in VGA mode
(no special capabilities of the VRAMs are required or used); all VGA
operations are implemented via the VRAM random access port. (Wingine
pinouts are defined such that future implementations may be extended
to take advantage of the VRAM serial port in VGA mode.) In 'Windows
Acceleration' mode, the VRAM random access ports are driven by the
system memory controller; the Wingine chip does not have access to the
VRAMs, but performs all VRAM serial data shift operations and provides
HSYNC and VSYNC for the display monitor. In 'Windows Acceleration'
mode, the system performs all data transfer operations based on
information provided from the Wingine chip.
The result is very high performance, since the entire random port
bandwidth is available for CPU access and the VRAMs may always be
accessed at full memory speed. In addition, memory may be accessed at
the full width of system memory (16 or 32 bits). The frame buffer may
be accessed as a linear array of pixels (in 'packed- pixel' format)
anywhere in the system memory space.
Another major advantage is the ability to accept 32 bits of serial
data from the VRAMs and convert it into an 8-bit video data stream
compatible with a standard low-cost VGA RAMDAC. This capability
removes the requirement for an expensive RAMDAC, allowing
implementation of cost effective, high performance graphics system.
Wingine directly supports 4bpp (nibble) and 8bpp (byte) modes with
standard VGA 8-bit RAMDACs which are available up to 80 MHz. 16bpp
mode may be supported with an extended capability RAMDAC such as a
Sierra SC11482, 483, or 484. Wingine can also support various types of
high performance and extended capability RAMDACs with 32-bit parallel
data input ports. These RAMDACs typically support pixel rates to 135
MHz and modes of 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, and / or 24bpp. All
known RAMDACs support these modes lsb first (e.g., nibble modes shift
the first pixel out of bits 0-3 of the first byte in memory, the
second pixel out of bits 4-7, etc). All of these modes up to 16bpp
are also supported in the XGA ('lsb first' is referred to as 'Intel
order' in IBM's XGA documentation). Therefore, for compatibility,
pixel shift order is always lsb first and pixels are always stored in
Wingine memory as a linear array of n-sized elements starting with
bit-0 of byte 0.
DISPLAY MEMORY CONFIGURATIONS
The VRAM frame buffer may be implemented with two, four, or eight
256Kx4 (1Mb) or two or four 256Kx8 (2Mb) VRAMs, accessed as 1 bank of
32-bit memory in 386 DX or 486 systems or as 2 banks of 16-bit memory
in 386 SX systems. This provides 1MB of display memory, which is
adequate for support of 1024x768 at 8bpp (256-color). This amount of
memory, using split buffer VRAMs and a Sierra RAMDAC (or equivalent),
will also support 16bpp modes up to 800x600.
Wingine allows 512KB upgradable to 1MB of display memory in 386 SX
(16-bit) systems by optionally populating the upper bank. The 512KB
configuration supports 1024x768 at 4bpp (16-color) and 640x480 at 8bpp
(256-color). If word interleaving is done in 16-bit systems, the
memory map is identical between 16 and 32 bit systems (and the same
drivers may be used). Wingine is designed to also handle
non-word-interleaved 2 bank 16-bit memory maps, if word interleaving
is not implemented by the system.
If 256Kx4 VRAMs are used, 512KB of display memory (upgradable to 1MB)
may also be implemented by optionally populating the upper nibble of
each byte. In this configuration, the system would always manipulate
display memory assuming 8bpp; screen display would be 16-color with 4
VRAMs installed and 256-color with 8 VRAMs installed (the RAMDAC pixel
mask register would be set to mask out the upper 4 bits of video data
in 4-VRAM mode).
Wingine will support 24bpp modes up to 640x480 in 1MB configurations,
but a RAMDAC must be used which allows packing R, G, & B every 3 bytes
and AT&T 206491 RAMDACs. The Bt482 support this type of pixel
packing. However Wingine will support 24bpp modes up to 640x400 if the
RAMDAC ignores one byte out of every four. Many 32-bit input RAMDACs
(Bt484 / 485, TI 34075 / 34076) support 24bpp mode in this fashion (by
ignoring the upper byte of the 32-bit input). Since only one pixel is
input to the RAMDAC every shift clock, the maximum pixel rate in this
mode is limited by the VRAM shift clock rate: 33 MHz for '-10' (100ns)
VRAMs and 40 MHz for '-8' (80ns) VRAMs).
Wingine supports interlaced displays at 1024x768 resolution. Wingine
maintains a linear address mapping scheme so that software drivers are
independent of whether the display is interlaced or not.
Wingine is compatible with VRAM memory configurations larger than 1MB,
if implemented by the system as either multiple banks of 32-bit memory
using '256K x N' VRAMs or single banks of 32-bit memory using '512K x
N' or '1M x N' VRAMs. These configurations would typically be
implemented with 32-bit input extended-function, high-performance
RAMDACs and support high resolutions (e.g., 1280x1024) and/or
high-color modes (16bpp and 24bpp).
SYSTEM SUPPORT REQUIREMENTS
To implement a Wingine-based Graphics sub-system, the system memory
controller must be able to map a bank (or banks) of VRAMs into the
system memory space. The memory controller must be aware of the
differences between VRAMs and DRAMs for random access port control
(the VRAM serial port is controlled by Wingine). Wingine support
exists in the CS4021 486 CHIPSet. Chips and Technologies plans to
provide Wingine support in all future Systems Logic CHIPSets and
SYSTEMSets to allow Wingine to interface directly to those products.
Extensions are also planned for all current CHIPSets and SYSTEMSets.
MEMORY INTERFACE
Two types of memory subsystems can be designed with Wingine. In the
first type, 2 or 4 DRAMs can be used for VGA compatible modes. For
Wingine modes, separate VRAMs are used. In this implementation, VGA
memory and 'Wingine mode' memory are separate. No external buffers
are required to isolate the two memory buses.
In the second type of memory subsystem, a shared memory bus is used
for a cost effective implementation. In this case, only VRAMs are
used. In VGA mode, Wingine controls video memory. In 'Wingine' mode,
the system memory controller has control over video memory. External
buffers are required to isolate the two buses - the Wingine memory bus
and the system memory bus. Refer to the following section for
additional details.
Wingine can support up to 2 Mbytes of display memory. It can also
support 256 Kbyte and 512 Kbyte memory configurations. The following
table shows a matrix of resolution and memory requirements. This
table assumes a shared memory architecture. It is important to
buffers SCLK with a fast buffer when 2 Mbyte configuration is used.
Resolution Memory
VGA Mode 640x480 16 Colors 256 Kbytes
800x600 16 Colors 256 Kbytes
640x480 256 Colors 512 Kbytes
1024x768 16 Colors 512 Kbytes
Wingine Mode 640x480 256 Colors 512 Kbytes
800x600 256 Colors 512 Kbytes
1024x768 256 Colors 1 Mbyte
640x480 16 bits/pixel 1 Mbyte
640x480 24 bits/pixel 1 Mbyte
800x600 16 bits/pixel 1 Mbyte *
1024x768 16 bits/pixel 2 Mbyte**
1280x1024 256 colors 2 Mbytes
>* Requires Split - Buffer VRAMs.
>** Requires Bt484 compatible DAC.
RECOMMENDED MEMORY CHIPS
Standard Split Buffer
Micron MT42C4256
Mitsubishi 442256
Toshiba 524256
NEC 42273
SYSTEM INTERFACE
The 64200 Wingine chip is tightly coupled to system chipsets from
Chips and Technologies. This tight coupling between Wingine and the
system chipset results in a very high performance Windows
architecture. The Wingine graphics controller can be interfaced to
two high performance CHIPSets from Chips & Technologies - the CS4021
and CS82310 chipsets.
****Wingine/CS4021 Interface:...
****Wingine/CS82310 Interface:...
****More:...
***Versions:...
***Features:...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
**82C591/2 3/486 <Mar92...
**82C593 3/486 [no datasheet] <May92...
**82C596/A 3/486 Writeback Cache [no datasheet] <11/11/92...
**?????? 486 EISA chipset [no datasheet] <Feb93...
**82C599 PCI-VLB Bridge [no datasheet, some info] ?
82C599 PCI-VLB Bridge referenced in:
http://web.mit.edu/netbsd/src/sys/dev/pci/pcidevs
from:
https://web.archive.org/web/20050313090427/http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html
"The Contaq Chipset (Contaq: 1080/4224) (8/27/95)
The Contaq 82C599 is paired with one of their 486VL chipsets (82C596
or 82C597) and bridges directly from the 486 CPU to the PCI bus.
Paraphrased from the Contaq spec.:
The 82C596 system controller provides the CPU interface, VESA bus
interface, ISA bus controller, etc. The 82C599 PCI controller provides
the bridge between PCI master/slave agent and the ISA/VESA standard
expansion bus; it arbitrates all the bus transactions between host
CPU, PCI agent, VESA device, and ISA device.
(Which sounds to me like the PCI bus is attached to the VL bus, rather
than to the CPU, which will cause PCI performance degradation.)"
**82C693 PCI-ISA Bridge [no datasheet] ?...
*Efar Microsystems [no datasheets, some info]...
**EFAR-8290WB 386/486 Writeback PC/AT Chipset [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**82EC798 386/486 Writeback PC/AT Single Chip [no datasheet] ?
**Other:...
*ETEQ...
**?????? "Cougar/Bobcat" 386DX/486DX chipset [no datasheet] cNov91...
***Notes:...
***Configurations:...
**?????? "Bengal" 386DX/486 (WriteBack) [no datasheet] cNov91...
***Notes:...
***Configurations:...
**ET2000 386/486 WB Chipset ?...
***Info:...
***Configurations:...
***Features:...
**ET6000 "Cheetah" 486DX/SX Non-Cache System <Apr92...
***Info:...
***Configurations:...
***Features:...
**ET9000 "Jaguar" 486 Write Back Cache AT Single Chip <Jun92...
***Info:...
***Configurations:...
***Features:...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet] ?...
***Configurations:...
**82C390SX "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
***Notes:...
**66x8 VIA clones [no datasheet] ?...
***Notes:...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel
**IBM PC/XT/AT Chip Sets...
***Datasheets:...
***Read Me:...
***Overview (History):...
***Summary of sections:...
***§1: Intel MCS-8x/iAPX Microprocessor families:...
***§2: Intel Chip Specifications 1975 - Jan 1982:...
***§3: IBM PC/XT: Original system chips: ...
***§4: Intel Chip Specifications Jan 1982 - Jan? 1984...
***§5: IBM AT: Original system chips:...
***§6: Intel Chip Specifications Jan? 1984 - 1989...
**82230/82231 High Integration AT-Compatible Chip Set(ZyMOS) c:Aug88...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82310 Micro Channel Compatible Peripheral Chip Set 04/21/88...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82311 High Integration MCA Compatible Perip. Chip Set 11/14/88...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82320 MCA compatible Chipset [no datasheet] 04/10/89...
***Notes:...
**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82350 EISA Chip Set 07/10/89...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82350DT EISA Chip Set 04/22/91...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
***Notes:...
***Info:...
***Versions:...
***Configurations:...
***Features:...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
***Notes:...
***Info:...
***Configurations:
Parts:
82439TX System Controller (MTXC) and the
82371AB PCI ISA IDE Xcelerator (PIIX4)
82439TX + 82371AB
***Features:...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
***Notes:...
***Info:...
****General:...
****82454KX/GX PCI Bridge (PB):
The 82454KX/GX PB are single-chip PC-compatible host-to-PCI bridges. A
rich set of Host-to-PCI and PCI-to-Host bus transaction translations
optimize bus bandwidth and improve system performance. All ISA and
EISA regions are supported. Three programmable memory gaps can be
created—a PCI Frame Buffer Region and two general-purpose memory gaps
(the Memory Gap Region and the High Memory Gap Region). The PB has a
synchronous interface to the Pentium Pro processor bus and supports a
derived clock for the synchronous PCI interface. The PB generates and
checks ECC over the host data bus (82545GX only), and generates and
checks parity over the address and request/response signal lines (both
82454KX and 82454GX). The PB also checks address and data parity on
the PCI bus. For the 82454GX, two PBs can be used in a system.
The Intel 450KX/GX PCIsets may contain design defects or errors known
as errata. Current characterized errata are available upon request.
3.0 PB FUNCTIONAL DESCRIPTION
This section describes the PB functions and hardware interfaces
including the I/O and Memory Map, Host bus, PCI bus, and Dual-bridge
Architectures. Data Integrity and Error Handling are covered. Clock,
Reset, and PB configuration are also covered.
3.1 Memory and I/O Map
The 82454KX/GX PB provides the interface between the host bus and the
PCI bus. Memory transactions can be sent from the PCI bus to the host
bus and from the host bus to the PCI bus. Gaps and positive decode
ranges can be programmed via the configuration registers. For the
82454KX, I/O transactions can be sent from the host bus to the PCI
bus. However, I/O transactions can not be sent from the PCI bus to the
host bus.
----------------------------------------------------------------------
For the 82454GX, both memory and I/O transactions can be sent from
the PCI bus to the host bus and from the host bus to the PCI
bus. Memory and I/O gaps and positive decode ranges can be
programmed via the configuration registers.
----------------------------------------------------------------------
If an access is enabled to be forwarded from the host bus to the PCI
bus, the corresponding access on the PCI bus is ignored (not forwarded
to the host bus). Conversely, if an access is enabled to be forwarded
from the PCI bus to the host bus, the corresponding access on the host
bus is ignored (not forwarded to the PCI bus).
The PB and MC perform a positive address decode of each host
transaction and one default device handles the unclaimed
transactions. In a standard PC system, unclaimed transactions are sent
to the ISA bus. Thus, the PB (Compatibility PB in an 82454GX dual PB
system) is the default responder on the host bus.
3.1.1 MEMORY ADDRESS MAP [see datasheet]
3.1.2 I/O ADDRESS MAP [see datasheet]
3.2 Host Bus Interface
The Pentium Pro processor bus provides an efficient, reliable
interconnect between multiple Pentium Pro processors and the PB and
MC. The bus provides 36 bits of address, 64 bits of data, protection
signals needed to support data integrity, and the control signals to
maintain a coherent shared memory in the presence of multiple caches.
The Pentium Pro processor bus achieves high bus efficiency by
providing support for multiple, pipelined transactions and deferred
replies. A single Pentium Pro processor may have up to four
transactions outstanding at the same time, and can be configured to
support a total of either one or eight transactions active on the
Pentium Pro processor bus at any one time. The PB supports up to eight
active transactions on the host bus (In-Order Queue depth of
8). During the host bus reset and configuration, all host bus devices
are configured to support either one or eight transactions in their
In-Order Queue.
The number of transactions that can target a particular bus client is
configured separately from the total number of transactions allowed on
the bus. The PB accepts up to four transactions into the Outbound
Request Queue that target its associated PCI bus.
The PB provides four 32-byte buffers for outbound data (host-to-PCI
writes or PCI reads from the host bus), and four 32-byte buffers for
inbound data (PCI-to-host writes or CPU reads from PCI).
As a host bus master, the PB does not support deferred responses. The
EXF1# extended function signal (Defer Enable) will never be asserted
for a host transaction initiated by the PB.
The host bus supports ECC over the data bus, and parity protection
over the address, request, and response lines. The PB generates and
checks ECC over the data lines (82454GX only), and generates and
checks parity over the address and request/response signal lines (both
82454KX/GX). Note, ECC generation and checking on the data lines and
parity generation and checking on the request/response lines can be
enabled or disabled during system configuration.
3.3 PCI Bus Interface
The PB has a standard master/slave PCI bus interface. All legal PCI
(PCI specification 2.0) bus transactions are supported. PCI cycle
termination and error logging/reporting are discussed in the Data
Integrity and Error Handling section. The PCI arbitration unit is not
implemented in the PB.
PCI Locks. Systems which support PCI initiate locks (either inbound
locks or peer-to-peer) must configure the arbiter for full bus locks
rather than resource locks. The PB will not recognize resource locks
made by peer-to-peer accesses. When a PCI master asserts LOCK# while
targeting the PB, the locked PCI transactions are converted to locked
host bus transactions. The host bus lock continues as long as the PCI
master asserts LOCK# for exclusive access to the PB. The host bus lock
is assisted by the bridge continuing to assert BPRI# as long as the
PCI bus is asserting resource lock to the bridge. Additional locked
CPU transactions are issued if the PCI master continues to burst.
In systems in which target abort reporting is disabled, the write
portion of a lock will be committed even when the read portion is
aborted.
Host Bus Locks. Any transactions that target the bridge during a host
bus lock are converted into a similar PCI lock transaction. The lock
on the PCI bus is held until the host bus lock is released. Locks
over the Frame Buffer region can be disabled through a mode bit in the
PCI Frame Buffer Range Register.
Indivisible Operations. CPU initiated read operations that cross a
Dword boundary (e.g., Read 8 Bytes, Read 16 Bytes, etc.) are
indivisible operations on the host bus. However, since the PCI
protocol allows a target device to disconnect at any point in a
transfer sequence, these operations must be locked indivisible on the
PCI bus. The PB optionally locks all CPU initiated reads that cross a
Dword boundary. This mode is enabled by setting the Lock Atomic Reads
in the PB Configuration Register. CPU initiated Write operations
(e.g., Write 8 Bytes, Write 16 Bytes, etc.) are indivisible operations
on the host bus. However, these accesses can not be made indivisible
on the PCI bus because the PCI Specification states that the first
transaction of a locked operation must be a read. Therefore, software
must not rely upon the atomicity of CPU initiated write transactions
greater then 32 bits once they are translated to the PCI bus.
Software Generated Special Cycles. This optional feature is not
supported by the 450KX/GX PCIset.
3.4 Data Integrity and Error Handling
Several data integrity features are included in the PB. These include
ECC on the host data bus (450GX only), parity on the host address,
parity on the CPU Request/Response signals, and parity on the PCI
bus. Error logging (setting a status bit) and reporting (generating an
error signal) are controlled by the PCICMD Register (04–05h), PCISTS
Register (06–07h), ERRCMD Register (70h), ERRSTS Register (71h),
EXERRCMD Register (C0–C3h), and EXERRSTS Register (C4–C7h).
3.4.1 HOST BUS ERRORS [see datasheet]
3.4.2 PCI BUS ERRORS [see datasheet]
3.5 Dual PB Architectures (82454GX Only)
----------------------------------------------------------------------
In a dual bridge system, one PB is configured as the default bridge
(Compatibility PB) after power-on RESET. The Compatibility PB
provides a path to the ISA bus devices needed in a PC-compatible
system such as the boot ROM. The Compatibility PB is the highest
priority bridge in a dual bridge system to ensure a fast enough
response time for ISA bus masters. See the Clocks, Reset, and
Configuration section for details on configuring a PB as the
Compatibility PB.
Multiple I/O APICs
In a dual PB system, the auxiliary PCI bus interrupt requests are
routed to the auxiliary bus I/O APIC. When booting the system with
one processor, the IRQ control logic is enabled, feeding the
interrupt request to the standard interrupt controller in the
ESC. When the system is in multiprocessor mode, the routing logic is
disabled after ensuring PB buffer coherency, and interrupt requests
are forwarded to the processors via the APIC bus. The Intel 82379AB
(SIO.A) may be utilized as a stand-alone I/O APIC device. However,
the additional logic for interrupt/memory consistency and the
interrupt steering logic is not provided in the SIO.A and must be
implemented externally.
Dual Bridge Arbitration for the Host Address Bus
The PB requests the host address bus with BPRI#. However, only one
bridge is allowed to drive BPRI# at a time. With two PBs, an
internal arbiter is used to establish bus ownership. This
arbitration is transparent to the CPU and other symmetric bus
agents.
In a two PB system, the compatibility PB acts as the arbitration
unit between it and the other PB, as shown in Figure 6 [see
datasheet]. When a PB is programmed to be the arbitration unit, its
IOGNT# is the input for the IOREQ# from the other bridge and IOREQ#
is the output to IOGNT# of the other bridge.
Figure 7 [see datasheet] shows the minimum arbitration timing in a
two bridge system. IOGNT# may assert later than shown and IOREQ# may
negate later than the two clocks after IOGNT# negates.
The arbiter bridge can assert BPRI# as long as it has not asserted
its IOREQ# (Grant to the other bridge) and BPRI# is not currently
driven. In turn, the other bridge, after receiving it’s IOGNT#,
samples BPRI# released before assuming ownership of BPRI#. This
allows the BPRI# arbitration to be performed in parallel with
another bridge transfer. This timing is shown in Figure 8. [see
datasheet]
Bridge-to-bridge misaligned (split) locks are not recommended and
could cause deadlock in systems.
Bridge-to-Bridge Communication
PB-to-PB communication is supported by the PB, but is not recom-
mended for optimal performance.
PB-to-PB transactions involving a standard bus bridge (SIO,
PCEB/ESC) require special precautions to avoid deadlock and latency
problems. The PB does NOT support PB-to-PB transactions from agents
that cannot be backed off such as those originating on an ISA or
EISA bus and targeting a device on a different PB’s PCI bus. Any
device that asserts FLSHBUF# must be targeting a device on the local
PCI bus or the host bus.
Dual PB Configuration (82454GX only)
During a power-on reset (PWRGD asserted), IOREQ# and IOGNT# provide
a unique identification number for each PB (PBID). The PBID is part
of the PB’s PCI Bridge Device Number and is available to programmers
via the BDNUM Register (offset 49h). The Dual PB system must have a
pull-up and a pull-down as shown in Figure 9. The encoding for these
signals is shown in Table 10. [see datasheet]
----------------------------------------------------------------------
3.6 Peripheral Operation and Performance
The 82454 PB is designed for optimum processor performance to get the
most out of a Pentium Pro processor’s capabilities. In systems with
multiple PCI devices, one must take into account the architecture of
the 82454 PB in order to maximize overall system performance.
3.6.1 MATCHING PERIPHERALS TO THE 450KX/GX [see datasheet]
3.6.2 DISTRIBUTING PERIPHERALS WITHIN THE I/O SUBSYSTEM
While this is not necessary for system operation, systems implementing
dual 82454 PBs have additional latitude to isolate high speed I/O
devices from competing system traffic initiated by the CPU.
All graphics and the vast majority of I/O space communication (such as
keyboard controller, system timer, and interrupt support) will be
directed to the primary PCI bus behind the Compatibility 82454
PB. (This is the bus with a subsequent connection via another bridge
to an ISA or EISA bus.) This processor traffic will compete with bus
mastering peripheral devices attempting to move data to and from
system memory. It is desirable then to place latency sensitive devices
behind the Auxiliary 82454 PB, to isolate them from competing CPU
traffic.
In a full system configuration, in which all PCI slots are occupied,
it is preferable to segregate peripherals intelligently. Limit the
primary PCI bus to graphics accelerators and SCSI RAID controllers,
leaving Auxiliary 82454 PB PCI slots free for latency-sensitive
devices such as network adapters. In systems connecting a large number
of network adapters, divide them evenly between the two busses to
minimize the amount of latency-sensitive competition at any one point
in the system.
3.6.3 PCI-TO-PCI BRIDGES [see datasheet]
3.6.4 BIOS PERFORMANCE TUNING [see datasheet]
3.7 Clock, Reset, and Configuration
3.7.1 SYSTEM CLOCKING [see datasheet]
3.7.2 SYSTEM RESET [see datasheet]
3.7.3 SYSTEM INITIALIZATION [see datasheet]
3.7.5 USING THE 82379AB SIO.A PCI-TO-ISA BRIDGE WITH THE 450KX/GX
There is an anomaly with systems that use the 82379AB (SIO.A) during
targeted PCI Resets. In addition, 450GX/KX systems can boot improperly
at power-up and react improperly to the assertion of the Pentium Pro
bus signal BINIT# signal (due to the assertion of PCIRST# via BINIT#).
The SIO.A drives SMI#, ALT_A20, INT, NMI, IGNNE#, ALT_RST#, and
STPCLK# low while PCIRST# is asserted low, and does not drive them
high until after PCI reset is released. An anomaly can exist with
these seven signals remaining low during and immediately after PCIRST#
is negated. The three instances in which this can cause an anomaly
are: during a targeted PCI Reset, and in a 450GX/KX-Pentium Pro
processor system, both during power-up and when BINIT# is asserted on
the Pentium Pro processor bus.
....[see datasheet]
3.8 Host to PCI Bus Command Translation [see datasheet]
3.9 PCI to Host Bus Command Translation [see datasheet]
****Memory Controller (MC) 82453KX/GX (DC), 82452KX/GX (DP), 82451KX/GX (MIC)...
***Configurations:...
****450KX:...
****450GX:...
*****Configuration 1: Single MC, Single PB (KX equivalent):...
*****Configuration 2: Single MC, Dual PB:...
*****Configuration 3: Dual MC, Single PB:...
*****Configuration 4: Dual MC, Dual PB:...
***Features:...
****General:...
****82454KX/GX PCI Bridge (PB):...
****Memory Controller (MC) 82453KX/GX (DC), 82452KX/GX (DP), 82451KX/GX (MIC)...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
***Notes:...
***Info:...
***Versions:...
***Features:...
**8289 Bus Arbiter (808x) c79...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
***Info:...
***Info:...
***Versions:...
***Features:...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
***Notes:...
***Info:...
***Versions...
***Features:...
**82335 High-Integration Interface Device For 386SX c:Nov88...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82360SL I/O Subsystem 10/05/90...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
***Notes:...
****Date:...
****Sources:...
****Limits on sourced text:...
****Late'93 - Almost no difference...
****November 94 - Spec Update and new SB variant...
****December 95 - Full datasheet...
****After 95 ...
***Info:...
****General...
*****All...
*****Mar'93, Late'93 only...
*****All...
****82375EB//82375SB PCI/EISA BRIDGE (PCEB)...
*****ALL...
*****Dec'95 only:...
*****ALL...
*****Mar'93, Late'93 only...
*****All...
*****Mar'93, Late'93 only...
*****All...
*****Mar'93, Late'93 only ...
*****All...
*****Mar'93, Late'93 only...
*****Dec'95 only...
*****All:...
*****Mar'93, Late'93 only...
*****Dec'95 only...
*****All:...
****82374EB//82374SB EISA SYSTEM CONTROLLER (ESC)...
*****Nov'94:...
*****Dec'95...
*****All...
*****Nov'94, Dec'95:...
*****All:...
*****Nov'94, Dec'95:...
*****All:...
*****Dec'95...
*****All...
*****Dec'95...
***Versions:...
***Configurations:...
***Features:...
****General:...
*****ALL...
****82375EB/82375SB PCI-EISA BRIDGE (PCEB)...
*****All...
*****Mar'93, Nov'94, Dec'95...
*****late'93...
*****All...
*****Nov'94, Dec'95:...
*****All:...
*****Late'93, Dec'95...
*****Dec'95...
****82374EB/82374SB EISA SYSTEM CONTROLLER (ESC)...
*****ALL...
*****Late'93, Nov'94, Dec'95...
*****Nov'94, Dec'95...
*****Dec'95...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
***Notes:...
***Info:...
****All...
****Oct'93...
****Dec'94...
****All...
****Mar'93...
****Dec'94...
****All:...
***Versions:...
****Errata:2 (Aug'93)...
***Features:...
****All...
****Mar'93, Oct'93...
****All...
****Dec'94...
****Mar'93...
****Oct'93...
****Dec'94...
**82379AB System I/O-APIC (SIO.A) <Dec94...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
***Notes:...
***Info: ...
***Versions:...
***Features:...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82384 Clock Generator and Reset Interface c86...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82385 32-bit Cache Controller for 80386 09/29/87...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82395DX High Performance Smart Cache 06/18/90...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82395SX Smart Cache 12/17/90...
***Notes:...
**82396SX Smart Cache 12/17/90...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485 Turbo Cache (and 485Turbocache) c90...
***Notes:...
***Info:...
***Versions:...
****485Turbocache module...
*****(Section: General Section Menu>Turbocache Issue> )...
*****(Section: General Section Menu>External Cache Adapters> )...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
**Notes:...
**GC101/102 12/16MHz PC/AT Compatible Chip Set c:Feb88...
***Info:...
***Configurations:...
***Features:...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0 c:Jul89...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**GCK113 80386 AT Compatible Chip Set c:oct89...
***Info:...
***Configurations:...
***Features:...
**GCK181 Universal PS/2 Chip Set c:Mar89...
***Info:...
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
***Notes:...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
***Info:...
***Configurations:...
***Features:...
**HT18 80386SX Single Chip c:Sep91...
***Info:...
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
***Info:...
***Configurations:...
***Features:...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
***Info:...
***Configurations:...
***Features:...
**HT25 3-volt Core Logic for 386SX c:Dec92...
***Info:...
***Configurations:...
***Features:...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
***Notes:...
**HTK320 386DX Chip Set c:Sep91...
***Info:...
***Configurations:...
***Features:...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
***Info:...
***Versions:...
***Features:...
**Other:...
*HMC (Hulon Microelectronics)...
**HMC82C206 Integrated Peripherals Controller (10MHz C&T 82c206) ?...
***Info:...
***Versions:...
***Features...
*Logicstar...
**SL600X PC / AT Compatible Chipset (10/12MHz) <Jul87...
***Info:...
****General:...
****SL6001 System Controller & SL6002 Memory Decode:...
****SL6003, SL6004 & SL6005 Address & Data Buffers:...
***Configurations:...
***Features:...
****General:...
**Support Chips:
**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87...
***Info:...
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
***Info:...
***Versions:...
***Features:...
**SL9020 Data Controller <oct88...
***Info:...
***Versions:...
***Features:...
**SL9025 Address Controller <oct88...
***Info:...
***Versions:...
***Features:...
**SL9090 Universal PC/AT Clock Chip <oct88...
***Info:...
***Versions:...
***Features:...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88
***Info:...
***Versions:...
***Features:...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
***Info:...
***Versions:...
***Features:...
**Other:...
*Motorola...
**IBM AT: MC146818 Real Time Clock <84...
***Info:...
***Versions:...
***Features:...
*OPTi...
**82C263 SCNB Single Chip Notebook c:92...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C281/282 Cache Sx/AT (386SX) <08/22/91...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C283 386SX System Controller c:91...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
***Info:...
***Configurations:...
***Features:...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
***Info:...
***Configurations:...
***Features:...
**82C381/382 HiD/386 (386DX) c:89...
***Info:...
***Configurations:...
***Features:...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
***Info:...
***Configurations:...
***Features:...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
***Notes:...
**82c463 SCNB Single Ship Notebook c:92...
***Info:...
***Configurations:...
***Features:...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
***Info:...
***Configurations:...
***Features:...
****MV...
****MVA...
****MVB:...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
***Notes:...
**82C491/392 486WB PC/AT Chipset <04/21/91...
***Info:...
***Configurations:...
***Features:...
**82C493/392 486SXWB <10/21/91...
***Info:...
***Configurations:...
***Features:...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
***Configurations:...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C495XLC PC/AT Chip Set c:93...
***Info:...
***Configurations:...
***Features:...
**82c496A/B DXBB PC/AT Chipset <Mar92...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
***Info:...
***Configurations:...
***Features:...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
***Notes:...
**82C499 DXSC DX System Controller c:93...
***Info:...
***Configurations:...
***Features:...
**82C546/547 Python PTM3V c:94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C556/7/8 Viper [no datasheet] ?...
***Configurations:...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
***Info:...
***Configurations:...
***Features:...
**82C571/572 486/Pentium c:93...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C576/7/8 Viper Xpress [no datasheet] ?...
***Configurations:...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
***Notes:...
***Info:...
***Configurations:...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
***Notes::...
***Info:...
***Configurations:...
***Features:...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
***Configurations:...
**82C681/2/6/7 386/486WB EISA c:92...
***Info:...
****General:...
****82C681 (EBC) EISA Bus Controller:...
****82C682 (MCC) Memory Cache Controller:...
****82C686 (ISP) Integrated System Peripheral:...
****82C687 (DBC) Data Bus Controller:...
***Configurations:...
***Features:...
****General:...
****82C681 (EBC) EISA Bus Controller:...
****82C682 (MCC) Memory Cache Controller:...
****82C686 (ISP) Integrated System Peripheral:...
****82C687 (DBC) Data Bus Controller:...
**82C683 386/486AWB EISA [no datasheet] ?...
***Notes:...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
***Notes:...
***info:...
***Configurations:...
***Features:...
**82C700 FireStar c:97...
***Info:...
***Configurations:...
***Features:...
**82C701 FireStar Plus c:97...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C750 Vendetta [no datasheet] ?...
***Notes:...
**82c801 SCWB2 DX Single Chip Solution c:92...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
***Notes:...
**82C802G/GP System/Power Management Controller (cached) c:93...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C895 System/Power Management Controller (cached) c:Sep94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
***Info:...
***Versions:...
***Features:...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
***Notes:...
***Info:...
***Versions:...
***Features:...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
**Other alias:...
**Notes:...
**Early Chipsets:...
**Later Chipsets:...
*SIS...
**85C211/2/5 286 chipset [no datasheet] ?...
***Notes:...
**85C310/320/330 'Rabbit' High performance 386DX chipset <91...
***Info:...
****General:...
****85C310 Cache/Memory Controller...
****85C320 Bus Controller:...
****85C330 Data Buffer:...
***Configurations:...
***Features:...
****General:...
****85C310 Cache/Memory Controller:...
****85C320 Bus Controller:...
****85C330 Data Buffer:...
**85C360 ISA 386DX Single Chip chipset [no datasheet] ?...
***Notes:...
**85C401/402 ISA 486DX/SX Cache chipset [no datasheet] ?...
***Notes:...
**85C406/5/411/420/431 EISA 386/486 Chipset [no datasheet] c91...
***Notes:...
**85C460 ISA 386DX/486 Single Chip [no datasheet] ?
**85C461 ISA 386DX/486 Single Chip [no datasheet] ?...
***Notes:...
**85C471/407 Green PC ISA-VLB 486 Single Chip <94...
***Info:...
***Configurations:...
***Features:...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95...
***Info:...
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
***Notes:...
***Info:...
****General:...
****85C501 PCI/ISA Cache Memory Controller (PCMC)...
****85C502 PCI Local Data Buffer (PLDB)
The SiS85C502 PCI Local Data Buffer(PLDB) provides a bi-directional
data buffering among the 64-bit Host Data Bus, the 64-bit Memory Data
Bus, and the 32-bit PCI Address/Data Bus. The PLDB incorporates three
Posted Write Buffers and two Read Buffers along the bridges of the
CPU, PCI and Memory buses. This buffering scheme smoothes the
differences in access latencies and bandwidths among three buses,
therefore improves the overall system performance. A four level/4DWs
deep write buffer (CTPPB) provides buffering on CPU write to PCI
bus. A one level/4QWs deep write buffer (CTMPB) is used for buffering
write data from the CPU to Memory. A one level/1QW deep write buffer
(PTMPB) is used to buffer PCI write to Memory data. A one QW Read
Buffer (CRMB) is used to latch CPU read Memory data and a one QW Read
Buffer (PRMB) is used to latch data in a PCI master read from L2 Cache
or DRAM cycle. During bus operation between the Host, PCI and Memory,
the PLDB receives control signals from the PCMC, performs functions
such as latching data, forwarding data to destination bus, data
assemble and disassemble.
****85C503 PCI System I/O (PSIO)...
***Configurations:...
***Features:...
****General:...
****85C501 PCI/ISA Cache Memory Controller (PCMC)...
****85C502 PCI Local Data Buffer (PLDB)...
****85C503 PCI System I/O (PSIO)...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
***Notes:...
***Info:...
****General:...
****SiS5501:...
****SiS5502:...
****SiS5503:...
***Configurations:...
***Features:...
****General:...
****SiS5501:...
****SiS5502:...
****SiS5503:...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
***Info:...
***Versions:...
***Features:...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
***Info:...
****General:...
****5501 PCI/ISA Cache Memory Controller (PCMC) ...
****5502 PCI Local Data Buffer (PLDB) ...
****5503 PCI System I/O (PSIO)...
***Configurations:...
***Features:...
****5501 PCI/ISA Cache Memory Controller (PCMC) ...
****5502 PCI Local Data Buffer (PLDB) ...
****5503 PCI System I/O (PSIO)...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
***Info:...
****General:...
****5511 PCI/ISA Cache Memory Controller (PCMC) ...
****5512 PCI Local Data Buffer (PLDB) ...
****5513 PCI System I/O (PSIO)...
***Configurations:...
***Features:...
****5511 PCI/ISA Cache Memory Controller (PCMC) ...
****5512 PCI Local Data Buffer (PLDB) ...
****5513 PCI System I/O (PSIO)...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
***Info:...
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
***Info:...
***Configuration:...
***Features:...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
***Info:...
***Configurations:...
***Features:...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
***Info:...
***Configurations:...
***Features:...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
***Info:...
***Configurations:...
***Features:...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
***Info:...
***Configurations:...
***Features:...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
***Info:...
***Configurations...
***Features:...
**55x SoC (System-on-chip) <03/14/02...
***Notes:...
***Versions:...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
***Notes:...
**5595 Pentium PCI System I/O <12/24/97...
***Notes:...
***Info:...
***Versions:...
***Features:...
**950 LPC I/O <07/16/99...
***Info:...
***Versions:...
***Features:...
**Other:...
***Video:...
***Various:...
**PII/III/Pro...
***Notes (Unverified Information!):...
***5600 c:Nov98...
***600 ?...
***620 c:Apr99...
***621 ?...
***630/630E/S c:Feb00...
***630ST/ET ?...
***633/633T c:Mar01...
***635/635T c:Mar01...
***640T c:Mar01 ...
**Athlon etc...
***Notes (Unverified Information!):...
***730S/SE c:Dec00...
***733 c:Apr01...
***735/735S c:Apr01...
***740 c:Nov01...
***745 c:Feb02...
***746/DX/FX c:Aug02...
***748 c:Aug03...
***741/741GX ?...
***M741 ? (mobile)...
*Symphony...
**SL82C360 'Haydn' 80386DX/SX chipset [no datasheet] c:Jun91...
***Notes:...
***Configurations:...
**SL82C460 'Haydn II' 80486 chipset [no datasheet] c:Jun91...
***Notes:...
***Configurations:...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91...
***Info:...
***Configurations:...
***Features:...
**SL82C490 'Wagner' 486? [no datasheet] ?...
***Notes:...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
***Notes:...
***Configurations:...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
***Info:...
***Versions:...
***Features:...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
***Info:...
***Versions:...
***Features:...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84...
***Notes:...
***Info:...
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
***Notes:...
**TACT82411 Snake Single-Chip AT Controller c90...
***Notes:...
***Info:...
***Configurations:...
***Features:...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
***Notes:...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
***Info:...
***Configurations:...
***Features:...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
***Notes:...
**Other:...
*UMC...
**UM82C*** (IBM/INTEL Direct replacement) c87...
**UM82C088 PC/XT Integration Chip <91...
***Info:...
***Configurations:...
***Features:...
**UM82C230 286AT MORTAR Chip Set <91...
***Info:...
***Configurations:...
***Features:...
**UM82C210 386SX/286 AT Chip Set <91...
***Info:...
***Configurations:...
***Features:...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
***Notes:...
**UM82C380 386 HEAT PC/AT Chip Set <91...
***Info:...
***Configurations:...
***Features:...
**UM82C480 386/486 PC Chip Set c91...
***Info:...
***Configurations:...
***Features:...
**UM82C493/491 ??????????????? [no datasheet] ?...
***Notes:...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
***Notes:...
***Configurations:...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
***Notes:...
***Configurations:...
**UM8890 Pentium chipset [no datasheet] ?...
***Notes:...
***Configurations:...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
***Info:...
***Versions:...
***Features:...
**UM82C852 Multi I/O For XT <91...
***Info:...
***Versions:...
***Features:...
**UM82C206 Integrated Peripheral Controller <91...
***Info:...
***Versions:...
***Features:...
**UM82c45x Serial/Parallel chips ?...
***Notes:...
**Other chips:...
***Video:...
***Disk:...
***Peripheral:...
***Other:...
*Unresearched:...
**A - D...
***Appian Technology...
***Atmel...
***Biostar...
***Citygate...
***Cyrix...
***Other...
**E - G...
***Evergreen?...
***Other...
**H - I...
***Hint...
***Other...
**J - R...
***Micro Integration...
***Micron...
****Micron Samurai (Dual Pentium II)...
****Micron Samurai DDR (Dual Pentium III)...
****Micron Samurai K7 (Dual Athlon)...
****Micron Mamba (Athlon)...
****Micron Shogun (Athlon)...
****Micron Scimitar (Athlon)...
***Oak...
***Other:...
**S...
***Shasta...
***SARC...
***ServerWorks (Reliance Computer Corporation)...
****Serverset III LE ...
****Serverset III HE [NB6536] ...
****Serverset III WS ...
****Serverset III HESL ...
***Sun Electronics (SUNTAC) ...
***Syslogic...
***Other...
**T - Z...
***Toshiba ...
***UniChip ...
***USA...
***Other...
*VIA
**SL9XXX FlexSet family General information...
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS
**ZyMOS POACH ...
**Other:...
*General Sources:...
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