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***Info:
The CS8231 TURBO CACHE BASED 386/AT CHIPSet is a seven chip VLSI
implementation of most of the system logic to implement a CACHE BASED
iAPX 386 based system. The CHIPSet is designed to offer a 100% PC AT
compatible integrated solution. The flexible architecture of the
CHIPSet allows it to be used in any iAPX386 based system design, such
as CAD/CAE workstations, office systems, industrial and financial
transaction systems.
The CS8231 CHIPSet combined with CHIP's 82C206, Integrated Peripherals
Controller, provides a complete PC AT compatible system using only 40
components plus memory devices.
The CS8231 CHIPSet consists of one 82C301 Bus Controller, one 82C307
Integrated CACHE/DRAM controller, one each of 82A303 and 82A304
Address Bus Interfaces, two 82B305 Data Bus Interfaces, and a 82A306
Control Signal Buffer.
The CHIPSet supports a local CPU bus, a 32-bit system memory bus, and
AT buses as shown in the system diagram below. The 82C301 and 82A306
provide the generation and synchronization of control signals for all
buses. The 82C301 also supports an independent AT bus clock, and
allows for dynamic selection of the processor clock between the 16M
Hz, 20MHz, or 25MHz clocks and the AT bus clock. The 82A306 provides
buffers for bus control signals in addition to other miscellaneous
logic functions.
The 82C307 is a high performance and high integration CACHE/DRAM
controller designed to interface directly to the 80386 micro-
processor. It maintains frequently accessed code and data in high
speed memory, allowing the 80386 to operate at its maximum rated freq-
uency with near zero waitstates. By integrating DRAM control func-
tions on-chip, it supports simultaneous activation of cache and DRAM
access, thereby minimizing the cache miss cycle penalty. It has
hardware support to allow the user to designate up to four blocks (of
variable size from 2KB to 128KB) of main memory as non-cacheable
address space. This feature is important for compatibility issues
when operating in a multiprocessing or LAN environment, or where dual-
port memory is used, and to designate certain regions of video RAM as
non-cacheable. This feature eliminates the need to use very fast PALs
externally to decode non-cacheable regions and gives the user much
more flexibility. Optional EDC support logic is integrated on to the
82C307 which allows it to interface to any of the generically
available 32-bit Error Detection and Correction Circuits to realize a
highly reliable memory subsystem.
Cache coherency is maintained during DMA cycles by channeling all acc-
esses through the cache controller logic. During DMA read operations,
the cache RAM is not accessed and data is retrieved from the main
memory. During DMA write operations, if a cache hit is detected, the
cache RAM is updated and the corresponding tag validated. Cache
coherency is maintained at all times, with no performance penalty.
The 82C307 is available in a 100 pin PFP package.
The 82A303 and 32A304 interface between all address buses, and the
addresses needed for proper data path conversion. Two 828305 are used
to interface between the local, system memory, and at data buses. In
addition to having high current drive, they also perform the
conversion necessary between the different sized data paths.
***Configurations:...
***Features:...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
**82C591/2 3/486 <Mar92...
**82C593 3/486 [no datasheet] <May92...
**82C596/A 3/486 Writeback Cache [no datasheet] <11/11/92...
**?????? 486 EISA chipset [no datasheet] <Feb93...
**82C599 PCI-VLB Bridge [no datasheet, some info] ?...
**82C693 PCI-ISA Bridge [no datasheet] ?...
*Efar Microsystems [no datasheets, some info]...
**EFAR-8290WB 386/486 Writeback PC/AT Chipset [no datasheet] ?...
**82EC798 386/486 Writeback PC/AT Single Chip [no datasheet] ?
**Other:...
*ETEQ...
**?????? "Cougar/Bobcat" 386DX/486DX chipset [no datasheet] cNov91...
**?????? "Bengal" 386DX/486 (WriteBack) [no datasheet] cNov91...
**ET2000 386/486 WB Chipset ?...
**ET6000 "Cheetah" 486DX/SX Non-Cache System <Apr92...
**ET9000 "Jaguar" 486 Write Back Cache AT Single Chip <Jun92...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet] ?...
**82C390SX "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8 VIA clones [no datasheet] ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel
**IBM PC/XT/AT Chip Sets...
**82230/82231 High Integration AT-Compatible Chip Set(ZyMOS) c:Aug88...
**82310 Micro Channel Compatible Peripheral Chip Set 04/21/88...
**82311 High Integration MCA Compatible Perip. Chip Set 11/14/88...
**82320 MCA compatible Chipset [no datasheet] 04/10/89...
**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90...
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
***Other
Victronix 5806 chipset - 486
Victronix 586 chipset - 486
VD 88C898
*VIA
**SL9XXX FlexSet family General information...
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?
***Info:...
***Versions:...
***Features:...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
***Features:
o PCI/ISA Green PC Ready
- Supports separately powered 3.3V (5V tolerant) interfaces to
system memory, AGP, and PCI bus
- Supports 3.3V and sub-3.3V interface to CPU
- PC-97 compatible using VT82C586B South Bridge with ACPI Power
Management
o High Integration
- Single chip implementation for 64-bit Socket-7-CPU, 64-bit
system memory, 32-bit PCI and 32-bit AGP interfaces
- Apollo VP3 Chipset: VT82C597 or VT82C597AT system controller
and VT82C586B PCI to ISA bridge
- Chipset includes UltraDMA-33 EIDE, USB, and Keyboard / PS2-Mouse
Interfaces plus RTC / CMOS on chip
o Flexible CPU Interface
- Supports 64-bit Pentium, AMD 5k86, AMD 6k86 and Cyrix 6x86 CPUs
- CPU external bus speed up to 66 MHz (internal 233MHz and above)
- Supports CPU internal write-back cache
- System management interrupt, memory remap and STPCLK mechanism
- Cyrix 6x86 linear burst support
- CPU NA# / Address pipeline capability
- 4 cache lines of CPU/cache-to-DRAM post-write buffers
- 4 quadwords of CPU/cache-to-DRAM read-prefetch buffers
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support (with
global write enable feature)
- Flexible cache size: 0K / 256K / 512K / 1M / 2MB
- 32 byte line size to match the primary cache
- Integrated 10-bit tag comparator
- 3-1-1-1 read/write timing for PBSRAM access at 66 MHz
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access at
66 MHz
- Sustained 3 cycle write access for PBSRAM access or CPU to DRAM
and PCI bus post write buffers at 66 MHz
- Data streaming for simultaneous primary and secondary cache line
fill
- System and video BIOS cacheable and write-protect
- Programmable cacheable region and cache timing
o AGP Controller
- AGP v1.0 compliant
- Supports SideBand Addressing (SBA) mode (non-multiplexed
address/data)
- Supports 133MHz 2X mode for AD and SBA signalling
- Pipelined split-transaction long-burst transfers up to 533 MB/
sec
- Eight level read request queue
- Four level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
o GART
- One level TLB structure
- Sixteen entry fully associative page table
- LRU replacement scheme
- Independent GART lookup control for host / AGP / PCI master
accesses
o Intelligent PCI Bus Controller
- PCI buses are synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- 66 MHz PCI operation on the AGP bus
- PCI-to-PCI bridge configuration on the 66MHz PCI bus
- Separate data buffers for the two PCI buses
- Peer concurrency
- Concurrent multiple PCI master transactions; i.e., allow PCI
masters from both PCI buses active at the same time
- Allows PCI master access while ISA master/DMA is active
- PCI master snoop ahead and snoop filtering
- Five levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Forty-eight levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Supports L1/L2 write-back forward to PCI master read to minimize
PCI read latency
- Supports L1/L2 write-back merged with PCI master post-write to
minimize DRAM utilization
- Transaction timer for fair arbitration between PCI masters
(granularity of two PCI clocks)
- Symmetric arbitration between Host/PCI bus for optimized system
performance
- Complete steerable PCI interrupts
- PCI-2.1 compliant, 32 bit 3.3V PCI interface with 5V tolerant
inputs
o Advanced High-Performance DRAM Controller
- 66MHz DRAM interface
- Concurrent CPU and AGP access
- FP, EDO, SDRAM, and SDRAM-II
- 66MHz DDR (Double Data Rate) supported for SDRAM-II
(supports central and edge DQ, bidirectional DS, and optional
SDR write)
- Different DRAM types may be used in mixed combinations
- Different DRAM timing for each bank
- Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
- 6 banks up to 1GB DRAMs
- Flexible row and column addresses
- 64-bit data width only
- 3.3V DRAM interface with 5V-tolerant inputs
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) or EC (error checking only) for DRAM
integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
(14 MA lines)
- Supports maximum 8-bank interleave (i.e., 8 pages open
simultaneously); banks are allocated based on LRU
- Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Concurrent DRAM writeback
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing
for EDO DRAMs at 66 MHz
- 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for
SDRAMs at 66 MHz
- 5-2-2-2-3-2-2-2 back-to-back accesses for EDO DRAM at 66 MHz
- 6-1-1-1-3-1-1-1 back-to-back accesses for SDRAM at 66 MHz
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate, CAS-before-RAS refresh and refresh on
populated banks only
o Built-in NAND-tree pin scan test capability
o 3.3V, 0.5um, high speed / low power CMOS process
o 472 pin BGA Package
o Alternate pinouts available to optimally accommodate different PCB
form factors
- VT82C597 for ATX and NLX
- VT82C597AT for Baby AT and ATX
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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