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*_IBM...
*ACC Micro...
*ALD...
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***Configurations:
M1561 System Controller
M1535D I/O
M1543 PCI-to-ISA Bus Bridge
M1561 + M1535D
M1561 + M1543
see the M1541 Aladdin V & V+ section for details on the M1543.
see the M1535 section for details on the M1535D.
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
**AMD Am286ZX/LX (286 Embeded CPU + integrated peripherals) ?
**AMD Elan Series (386/486 Embeded CPU + integrated peripherals) ?
**AMD 640/645 (Pentium Based on VIA VT82C590) [some info] c97...
**Later Chipsets:...
*Chips & Technologies...
**CS8220 PC/AT compatible CHIPSet (82C201/C202/A203/A204/A205)cOct85...
**CS8221 NEW Enhanced AT (NEAT) (82C211/82C212/82C215/82C206) c86...
**CS8223 LeAPset [no datasheet] ?
**CS8225 CHIPS/250 PS/2 50/60 [no datasheet, some info] c88...
**CS8227 CHIPSlite (82C235/82C641) ?...
**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
**82C591/2 3/486 <Mar92...
**82C593 3/486 [no datasheet] <May92...
**82C596/A 3/486 Writeback Cache [no datasheet] <11/11/92...
**?????? 486 EISA chipset [no datasheet] <Feb93...
**82C599 PCI-VLB Bridge [no datasheet, some info] ?...
**82C693 PCI-ISA Bridge [no datasheet] ?...
*Efar Microsystems [no datasheets, some info]...
**EFAR-8290WB 386/486 Writeback PC/AT Chipset [no datasheet] ?...
**82EC798 386/486 Writeback PC/AT Single Chip [no datasheet] ?
**Other:...
*ETEQ...
**?????? "Cougar/Bobcat" 386DX/486DX chipset [no datasheet] cNov91...
**?????? "Bengal" 386DX/486 (WriteBack) [no datasheet] cNov91...
**ET2000 386/486 WB Chipset ?...
**ET6000 "Cheetah" 486DX/SX Non-Cache System <Apr92...
**ET9000 "Jaguar" 486 Write Back Cache AT Single Chip <Jun92...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet] ?...
**82C390SX "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8 VIA clones [no datasheet] ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel
**IBM PC/XT/AT Chip Sets...
**82230/82231 High Integration AT-Compatible Chip Set(ZyMOS) c:Aug88...
**82310 Micro Channel Compatible Peripheral Chip Set 04/21/88...
**82311 High Integration MCA Compatible Perip. Chip Set 11/14/88...
**82320 MCA compatible Chipset [no datasheet] 04/10/89...
**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90...
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
***Info:
The 82396SX Smart Cache (part number 82396SX) is a low cost, single
chip, 16-bit peripheral for Intel's i386 SX Microprocessor. By
storing frequently accessed code or data from main memory the 82396SX
Smart Cache enables the i386 SX Microprocessor to run at near zero
wait states. The dual bus architecture allows another bus master to
access the System Bus while the i386 SX Microprocessor operates out of
the 82396SX Smart Cache on the Local Bus. The 82396SX Smart Cache has
a snooping mechanism which maintains cache coherency with main memory
during these cycles.
The 823968X Smart Cache is completely software transparent, protecting
the integrity of system software. The advanced architectural features
of the 82596SX Smart Cache offer high performance with a cache data
RAM size that can be integrated on a single chip, offering the board
space and cost savings needed in an i386 SX Microprocessor based
system.
1.0 823968X SMART CACHE FUNCTIONAL OVERVIEW
1.1 Introduction
The primary function of a cache is to provide local storage for freq-
uently accessed memory locations. The cache intercepts memory
references and handles them directly without transferring the request
to the System Bus. This results in lower traffic on the System Bus and
decreases latency on the Local Bus. This leads to improved performance
for a processor on the Local Bus. It also increases potential system
performance by reducing each processor's demand for System Bus band-
width, thus allowing more processors or system masters in the system.
By providing fast access to frequently used code and data the cache is
able to reduce the average memory access time of the i386 SX
Microprocessor based system.
The 82396SX Smart Cache is a single chip cache subsystem specifically
designed for use with the i386 SX Microprocessor. The 82396SX Smart
Cache integrates 16KB cache, the Cache Directory and the cache control
logic onto one chip. The cache is unified for code and data and is
transparent to application software. The 82396SX Smart Cache provides
a cache consistency mechanism which guarantees that the cache has the
most recently updated version of the main memory. Consistency sup-
port has no performance impact on the i386 SX Microprocessor. Section
1.2 covers all the 82396SX Smart Cache features.
The 82396SX Smart Cache architecture is similar to the i486 SX
Microprocessor's on-chip cache. The cache is four Way SET associative
with Pseudo LRU (Least Recently Used) replacement algorithm. The line
size is 16B and a full line is retrieved from the memory for every
cache miss. A TAG is associated with every 16B line. The 82396SX Smart
Cache architecture allows for cache read hit cycles to run on the
Local Bus even when the System Bus is not available. 82396SX Smart
Cache incorporates a new write buffer cache architecture, which allows
the i386 SX Microprocessor to continue operation without waiting for
write cycles to actually update the main memory.
A detailed description of the cache operation and parameters is
included in Chapter 2.
The 82396SX Smart Cache has an interface to two electrically isolated
busses. The interface to the i386 SX Microprocessor bus is referred to
as the Local Bus (LB) interface. The interface to the main memory and
other system devices is referred to as the 82396SX Smart Cache System
Bus (SB) interface. The SB interface emulates the i386 SX
Microprocessor. The SB interface, as does the i386TM SX Micro-
processor. operates in pipeline mode.
In addition, it is enhanced by an optional burst mode for Line Fills.
The burst mode provides faster line fills by allowing consecutive read
cycles to be executed at a rate of up to one word per clock
cycle. Several bus masters (or several 82396SX Smart Caches) can share
the same System Bus and the arbitration is done via the SHOLD/SHLDA
mechanism (similar to the i486 SX Microprocessor).
Cache consistency is maintained by the SAHOLD/SEADS# snooping
mechanism, similar to the i486 SX Microprocessor. The 82396SX Smart
Cache is able to run, a zero wait state i386 SX Microprocessor
non-pipelined read cycle if the data exists in the cache. Memory write
cycles can run with zero wait states if the write buffer is not full.
The 82396SX Smart Cache organization provides a higher hit rate than
other standard configurations. The 82396SX Smart Cache, featuring the
new high performance write buffer cache architecture, provides full
concurrency between the electrically isolated Local Bus and System
Bus. This allows the 82396SX Smart Cache to service read hit cycles on
the Local Bus while running line fills or buffered write cycles on the
System Bus.
1.2 Features
1.2.1 823858X-LIKE FEATURES
o The 82396SX Smart Cache maps the entire physical address range of
the i386 SX Microprocessor (16MB) into an 16KB cache. Unified code
and data cache.
o Cache attributes are handled by hardware. Thus the 82396SX Smart
Cache is transparent to application software. This preserves the
integrity of system software and protects the users software
investment.
o Word and Byte writes, Word reads.
o Zero wait states in read hits and in buffered write cycles. All i386
SX Microprocessor cycles are non-pipelined (Note: The i386 SX
Microprocessor must never be pipelined when used with the 82396SX
Smart Cache - NA# must be tied to Vcc).
o A hardware cache FLUSH# option. The 82396SX Smart Cache will
invalidate all the Tag Valid bits in the Cache Directory and clear
the System Bus line buffer when FLUSH# is activated tor a minimum of
four CLK’s.
o The 82396SX Smart Cache supports non-cacheable accesses.
o The 82396SX Smart Cache internally decodes the i387 SX Math
Coprocessor accesses as Local Bus cycles.
o The System Bus interface emulates a i386 SX Microprocessor
interface.
o The 82396SX Smart Cache supports pipelined and non-pipelined system
interface.
o Provides cache consistency (snooping): The 82396SX Smart Cache
monitors the System Bus address via SEADS# and invalidates the cache
address if the System Bus address matches a cached location.
1.2.2 NEW FEATURES
o 16KB on chip cache arranged in four banks, one bank for each way. In
Read hit cycles, one word is read. In a write hit cycle, any byte
within the word can be written. In a cache fill cycle, the whole
line (16B) is written. This large line size increases the hit rate
over smaller line size caches.
o Cache architecture similar to the i486 SX Microprocessor cache: 4
Way set associative with Pseudo LRU replacement algorithm. Line
size is 16B and a full line is retrieved from memory for every cache
miss. A Tag Valid Bit and a Write Protect Bit are associated with
every Line.
o New write buffer architecture with four word deep write buffer
provides zero wait state memory write cycles. I/O, Halt/ Shutdown
and LOCK#ed writes are not buffered.
o Concurrent Line Buffer Cacheing: The 82396SX Smart Cache has a line
buffer that is used as additional memory. Before data gets written
to the cache memory at the completion of a Line Fill it is stored in
this buffer. Cache hit cycles to the line buffer can occur before
the line is written to the cache.
o In i387 SX Math Coprocessor accesses, the 82396SX Smart Cache drives
the READYO# in one wait state if the READYI# was not driven in the
previous clock.
Note that the timing of the 82396SX Smart Cache’s READYO# generation
for i387 SX Math Coprocessor cycles is incompatible with 80287
timing.
o An enhanced System Bus interface:
a) Burst Option is supported in line-fills similar to the i486 SX
Microprocessor. SBRDY# (System Burst READY) is provided in
addition to SRDY#. A burst is always a 16 byte line fill (cache
update) which is equivalent to eight word cycles.
b) System cacheability attribute is provided (SKEN#). SKEN# is used
to determine whether the current cycle is cacheable. It is used
to qualify Line Fill requests.
c) SHOLD/SHLDA system bus arbitration mechanism is supported. A
Multi i386 SX 82396SX Smart Cache cluster can share the same
System Bus via this mechanism.
f) Cache invalidation cycles supported via SEAD$#. This is used to
provide cache coherency.
o Full Local Bus/System Bus concurrency is attained by:
a) Servicing cache read hit cycles on the Local Bus while completing
a Line Fill on the System Bus. The data requested by the i386 SX
Microprocessor is provided over the local bus as the first word
of the Line Fill.
b) Servicing cache read hit cycles on the Local Bus while executing
buffered write cycles on the system bus.
c) Servicing cache read hit cycles on the Local Bus while another
bus master is running (DMA, other i386 SX Microprocessor, 82396SX
Smart Cache, i486 SX Microprocessor, etc...) on the System Bus.
d) Buffering write cycles on the Local Bus while the system bus is
executing other cycles. Write protected areas are supported by
the SWP# input. This enables caching of ROM space or shadowed ROM
space.
o No Post Input (NPI#) provided for disabling of write buffers per
cycle. This option supports memory mapped l/O designs.
o Byte Enable Mask (BEM) is provided to mask the processor byte
enables during a memory read cycle.
o A2oM# input provided for emulation of 8086 address wrap-around.
o SRAM test mode, in which the TAGRAM and the cache RAM are treated as
standard SRAM, is provided. A Tristate Output test mode is also pro-
vided for system debugging. In this mode the 82396SX Smart Cache is
isolated from the other devices in the board by floating all its
outputs.
o Single chip, 132 lead PQFP package, 1 micron CHMOS-IV technology.
***Versions:...
***Features:...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
***Features:
o Supports Intel/AMD/Cyrix/IDT Pentium CPU Host Bus at
66/75/83/95/100 MHz and 2.5/3.3V Bus Interface
− Supports the Pipelined Address of Pentium compatible CPU
− Supports the Linear Address Mode of Cyrix CPU
− 100/100, 95/95, 83/83, 75/75 and 66/66 MHz Synchronous
Host/DRAM clocking configuration
− 100/75, 95/75, 83/66, 66/100 and 66/83 MHz Asynchronous
Host/DRAM clocking configuration
− Supports Host Bus operation for integrated 3D VGA Controller
o Meets PC99 Requirements
o Supports PCI Revision 2.2 Specification
o Integrated Super AGP VGA for Hardware 2D/3D Video/Graphics
Accelerators
− Supports tightly coupled 64 bits 100MHz host interface to VGA
to speed up GUI performance and the video playback frame rate
− Built-in programmable 24-bit true-color RAMDAC up to 230 MHz
pixel clock
− Built-in reference voltage generator and monitor sense circuit
− Supports loadable RAMDAC for gamma correction in high color
and true color modes
− Built-in dual-clock generator
− Supports Multiple Adapters and Multiple Monitors
− Built-in PCI multimedia interface
− Flexible design for shared frame buffer or local frame buffer
architecture
− Shared System Memory Area 2MB, 4MB and 8MB
− Supports SDRAM and SGRAM local frame buffer and memory size up
to 8 MB
− Supports Digital Flat Panel Port for Digital Monitor (LCD Panel)
− Supports DVD H/W Accelerator
o Integrated Second Level ( L2 ) Cache Controller
− Write Back Cache Mode
− Direct Mapped Cache Organization
− Supports Pipelined Burst SRAM
− Supports 256K/512K/1M/2M Bytes Cache Sizes
− Cache Hit Read/Write Cycle of 3-1-1-1
− Cache Back-to-Back Read Cycle of 3-1-1-1-1-1-1-1
− Supports Single Read Allocation for L2 Cache
− Supports Concurrency of CPU to L2 cache and Integrated A.G.P.
VGA master to DRAM accesses
o Integrated DRAM Controller
− Supports up to 3 double sided DIMMs (6 rows memory)
− Supports 8Mbytes to 1.5 GBytes of main memory
− Supports Cacheable DRAM Sizes up to 256 MBytes
− Supports 1M/2M/4M/8M/16M/32M x N for 2-bank or 4-bank SDRAM
− Supports 3.3V DRAM
− Supports Concurrent Write Back
− Supports CAS before RAS Refresh, Self Refresh
− Supports Relocation of System Management Memory
− Programmable CS#, DQM#, SRAS#, SCAS#, RAMWE# and MA Driving
Current
− Option to Disable Local Memory in Non-cacheable Regions
− Entries GART cache to Minimize the Number of Memory Bus Cycles
Required for Accessing Graphical Texture Memory
− Programmable Counters to Ensure Guaranteed Minimum Access Time
for Integrated A.G.P. VGA, CPU, and PCI accesses
− Two Programmable Non-cacheable Regions
− Supports X-1-1-1/X-2-2-2 Burst Write Cycles
− Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
− Shadow RAM in Increments of 16 KBytes Built-in 8 Way
Associative/16
− Supports SDRAM 7/8-1-1-1 Burst Read Cycles
o Provides High Performance PCI Arbiter
− Supports up to 4 PCI Masters
− Supports Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead
- Supports Concurrency between CPU to Memory and PCI to PCI
- Supports Concurrency between CPU to 33Mhz PCI Access and 33Mhz
PCI to integrated A.G.P. VGA Access
- Programmable Timers Ensure Guaranteed Minimum Access Time for
PCI Bus Masters, and CPU
o PCI Bus Interface
- Supports 32-bit PCI local bus standard Revision 2.2 compliant
- Integrated write-once subsystem vendor ID configuration register
- Supports zero wait-state memory mapped I/O burst write
- Integrated 2 stages PCI post-write buffer to enhance frame
buffer write performance
- Integrated 256 bits read cache to enhance frame buffer read
performance
- Supports full 16-bit re-locatable VGA I/O address decoding
o Integrated Host-to-PCI Bridge
- Supports Asynchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Zero Wait State Burst Cycles
- Supports Pipelined Process in CPU-to-PCI Access
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Supports Memory Remapping Function for PCI master accessing
Graphical Window
o Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
- Supports Graphic Window Size from 4MBytes to 256MBytes
- Supports Pipelined Process in CPU-to-Integrated 3D A.G.P.
VGA Access
- Supports 8 Way, 16 Entries Page Table Cache for GART to enhance
Integrated A.G.P. VGA Controller Read/Write Performance
- Supports PCI-to-PCI bridge function for memory write from 33Mhz
PCI bus to Integrated A.G.P. VGA
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 12QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer with 2 QW Deep
- PCI-to-Memory Posted Write Buffer with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer with 8 QW Deep
- CPU-to-VGA Posted Write Buffer with 4 QW Deep
o Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for Windows 98 Compliant
Controller
- Plug and Play Compatible
- Supports Scatter and Gather
- Supports Dual Mode Operation - Native Mode and Compatibility
Mode
- Supports IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Supports Multiword DMA Mode 0, 1, 2
- Supports Ultra DMA 33/66
- Two Separate IDE Bus
- Two 16 DW FIFO for PCI Burst Transfers.
o Supports NAND Tree for Ball Connectivity Testing
o 576-Balls BGA Package
o 3.3V Core with mixed 2.5V, 3.3V and 5V I/O CMOS Technology
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
**SL82C360 'Haydn' 80386DX/SX chipset [no datasheet] c:Jun91...
**SL82C460 'Haydn II' 80486 chipset [no datasheet] c:Jun91...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91...
**SL82C490 'Wagner' 486? [no datasheet] ?...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
**UM82C*** (IBM/INTEL Direct replacement) c87...
**UM82C088 PC/XT Integration Chip <91...
**UM82C230 286AT MORTAR Chip Set <91...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
**A - D...
**E - G...
**H - I...
**J - R...
**S...
**T - Z...
*VIA
**SL9XXX FlexSet family General information...
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?
***Info:...
***Versions:...
***Features:...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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