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**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
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**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
**IBM PC/XT/AT...
*ACC Micro...
**Notes:...
**ACC82010 AT Chip Set (286 12.5/16MHz Max) c88...
***info:...
***Configurations:...
***Features:...
**ACC82020 Turbo PC/AT Chip Set (286/386SX 25MHz Max) c88...
***Notes:...
***info:...
***Configurations:...
***Features:...
**ACC82021 Turbo PC/AT Chip Set (286/386SX 25MHz Max) >88...
***Notes:...
***info:...
***Configurations:...
***Features:...
**ACC82300 386 AT Chip Set (386DX) c88...
***Info:...
***Configurations:...
***Features:...
**ACC82C100 Single-Chip PC/XT Systems-Controller c90...
***Info:...
***Configurations:...
***Features:...
**ACC83000 Model 30 Integrated Chip Set (MCA) c88...
***Info:...
***Configurations:...
***Features:...
**ACC85000/A Model 50/60 Chipset (MCA) c88...
***Info:...
***Configurations:...
***Features:...
**ACC1000 Turbo PC/XT Integrated Bus and Peripheral Ctrl. 04/02/88...
***Info:...
***Configurations:...
***Features:...
**ACC2036 Single Chip Solution 2036 (286/386SX) <Jul92...
***Info:...
***Configurations:...
***Features:...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT <Jul92...
***Info:...
***Configurations:...
***Features:...
**ACC2048 WB 486 Notebook/Embedded Single Chip [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96...
***Info:...
***Configurations:...
***Features:...
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
***Notes:...
***Configurations:...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
***Notes:...
***Info:...
***Configurations:...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
***Notes:...
***Info:...
***Configurations:...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
***Info:
[no general description]
[below is *selected* parts of the functional description]
The ACC2087 supports the 486 and 386DX CPUs. The CPU interface
selection is determined by detecting a pull up or pull down resistor
on pin 172 (M486) during the reset period. A pull up resistor on pin
172 will trigger the ACC2087 operating in the 486 mode. A pull down
resistor on pin 172 will trigger the ACC2087 operating in the 386DX
mode.
80387 Interface Control:
The 80387 interfaces directly to the 386DX with the error-reporting
logic built in the ACC2087. A coprocessor error is sent to the
ACC2087, generating an interrupt request to the CPU, followed by a
service request. A write operation to I/O port 0F0 will clear the
interrupt request.
Clock Throttling:
To further reduce the power consumption in the Notebook system, the
ACC2087 supports another mode called Clock Throttling. After scaling
the CPU clock, the ACC2087 can periodically assert the STPCLK# request
which will force the CPU into Stop Grant State. Hence the CPU power
can be further reduced.
Local Bus Peripheral Support Master / DMA Mode and SMM Support in
Local Bus Cycle:
The ACC2087 supports VL-Bus with master and DMA modes. To further
enhance the flexibility, the local bus can be detected under System
Management Mode (SMM).
Intel System Management Mode Interface (SMM)
System Management Mode (SMM) is designed to handle power management
interrupts that are totally transparent to the existing programs,
operating systems and CPU operation modes. The ACC2087 contains
dedicated logic to interface with SMM implemented by the Intel
SL-enhanced 486 for battery-powered portable computers. The ACC2087
utilizes the DRAMs located between segments A000h and B000h as the
separate SMM memory (SMRAM) required by SMM functions.
Power Management Features:
The ACC2087 provides a powerful mechanism of system power management
that is completely transparent to the operating system and application
software. It was designed from the system level to synthesize and
manage power consumption for the lowest power operation while
maintaining system performance in the portable system.
High Performance Cache Controller:
The integrated ACC2087 cache controller supports a direct mapped cache
from 32 Kbytes up to 2 Mbytes in size. The direct mapped architecture
means that a specified line in the cache is capable of caching only a
certain range of memory addresses. The low order address bits choose
the location (index) while the high order address bits (tag) identify
the entry.
As for write policy, the ACC2087 supports either write through or
write back cache implementations. In addition, the ACC2087 cache
architecture can be used in both 386DX and 486 applications. For a
386DX design, the ACC2087 cache controller can be used to support a
primary cache. In a 486 AT system, if the internal cache of the 486 is
enabled, the ACC2087 direct mapped cache can be used as secondary
cache.
Memory Controller:
The Memory Controller is a key feature of the ACC2087. This versatile
circuit provides complete control of up to 64 megabytes of system
DRAM. In any control mode, it generates up to four Row Address Strobes
(RAS#0-3) and one Memory Write Enable signal (WEN#). The Memory
Controller also provides the interface to transfer control to a DMA
controller or an AT Bus master.
The ACC2087 Memory Controller supports 256KB, 512KB, 1MB and 4MB DRAM
devices. The ACC2087 provides all control signals and programmable
control to support 256Kx1, 512Kx1, 1Mx1, 1Mx4, 4Mx1 and 4Mx4
(symmetrical only).
Memory Mapping:
Memory Mapping translates system RAM within the 640 KB to 1MB range,
which is reserved for the system ROM and BIOS application, to an
accessible address range above the physical RAM space. For example, if
4 MB of memory are installed, and the memory mapping feature is on,
the DRAMs in the 640 KB to 1MB range are mapped to an address
immediately above 4 MB.
Shadow RAM
Shadow RAM provides an option to transfer BIOS or video-extension BIOS
program codes into system RAM. This option provides significant
performance improvement for applications requiring intensive BIOS
calls.
Shadow RAM implements an alternate BIOS source by copying the complete
EPROM program code into system RAM. This is referred to as "shadowing"
because the DRAM and EPROM are both located in the same physical
address space. This change is transparent to the rest of the
system. ROM can then be disabled, allowing the RAM to respond in its
place.
Interrupt Controllers
There are two programmable interrupt controllers for the ACC2087. They
are fully compatible with Intel's 8259 controller, providing up to 15
interrupt sources (14 external and 1 internal). The internal line
connects to the 8254 Counter 0 output.
These interrupt controllers prioritize interrupt requests to the CPU.
DMA
The ACC2087 has two DMA controllers, compatible with the Intel 8237,
which provide a total of seven external DMA channels.
Combined with the Memory Mapper, each DMA channel has a 24-bit address
output to access data throughout the 64 megabyte system address space.
Memory Mapper
The ACC2087 has a built-in logic equivalent to the 74LS612, generating
the upper address bits during a DMA cycle.
Timer/Counter
The ACC2087 provides three internal counters, which are compatible
with the 8254. The clock input for each counter is tied to a clock of
1.19 MHz, which is derived by dividing the 14.318 MHz crystal input by
12. The output of Counter 0 is connected to the IRQ0 input of
interrupt controller 1. Counter 1 initiates a refresh cycle and
Counter 2 generates sound waveforms for the speaker.
ACC2087 I/O Address Map
The ACC2087 I/O address decode is fully compatible to the IBM PC/AT
requirements. The ACC2087 has decoded the I/O address range from 000
to 0FF to allow users to use the I/O areas not used by the IBM PC/AT.
PIO
The PIO is the system configuration to control the speaker port. It
also has circuitry to detect refresh. This condition can be read back
as Bit 4 of I/O Port 61h.
DMA Arbitration Logic
There are two possible sources for a hold request to the CPU. Either
the DMA controller issues a hold request or the output of Counter 1 in
the 8254 makes a low to high transition. The HOLD line is active when
either source is requesting a hold. The ACC2087 contains the logic to
do the arbitration.
Refresh Generation Logic
The ACC2087 contains circuitry to perform DRAM refresh cycle. Refresh
circuitry contains an 8-bit counter for address SA0-7 during a
refresh. In addition, three more address counter bits are presented
inside the ACC2087 to support refresh for DRAMs up to 4M bits.
Staggered Refresh Logic
The ACC2087 refresh logic works to perform a periodic refresh for both
system DRAM and extended RAM on the AT Bus. The ACC2087 initiates a
refresh cycle by driving its REFRESH# output low, and driving the
refresh address onto the MA Bus, simultaneously generating staggered
refresh pulses on the four RAS outputs. The RAS outputs are staggered
to reduce the current drain caused by the refresh operation. During
each refresh cycle, the ACC2087 drives the current refresh address
onto the AT address bus. This provides the refresh address for
extended memory.
NMI and Port B Logic
The ACC2087 contains non-maskable interrupt (NMI) signal generation
logic. An NMI can be caused by an I/O error or by a parity error. Port
B identifies the source of the error. At power up, the NMI signal is
masked off. NMI is enabled by writing to I/O address 070 with bit 7
low; NMI is disabled by writing to I/O address 070 with bit 7 high.
Bus Controller and Converter
The flexible ACC2087 Bus Controller provides all of the control logic
needed to interface to the CPU, alternate masters, local memory,
primary or secondary cache and the AT bus. Each access may be
initiated by the ACC2087 decoding the address and cycle type provided
on the local CPU bus. The cycle type is determined by monitoring the
signals D/-C, W/-R and M/-IO.
Turbo Speed Control Logic
The CPU clock frequency can be switched between CLKSRC and the AT
clock. The frequency switch can be generated through either hardware
or software. A TURBO pin is provided to support a front panel turbo
speed switch. TURBO high selects CLKSRC as the CPU clock. TURBO low
selects AT Bus clock as the CPU clock.
For power conservation, a standby mode clock control is provided. A
system needs to pre-select the standby frequency first, then BIOS will
monitor the activity of the system. If all pre-defined conditions of
the standby mode are satisfied, the system will go into the standby
mode by programming bit 3 of Register 8h to 1 or if the Turbo/Sleep
bit has been set to 1. The Turbo pin, when driven low, will force the
system into sleep mode.
OS/2 Optimization
The ACC2087 implements OS/2 optimization, which is a more efficient
way to switch back and forth between real and protected modes in an
OS/2 environment when frequent DOS calls are made. Conventional
methods require the processor to communicate with the integrated
/external keyboard controller in switching to protected mode and
activating gate A20.
With OS/2 optimization, the ACC2087 allows control of software CPU
reset and A20 gating through Port 92h.
Floppy Disk Drives
With the ACC2087, designers can build an IBM PC/XT or AT compatible
Floppy Disk Drive with fast access time, high reliability and low cost
per bit capability. The ACC2087 integrates the functions of a standard
floppy disk drive controller.
Data separator
Write precompensation circuit
Decode logic
Data rate selection
Clock generation
Drive interface drivers and receivers.
This integration greatly reduces the number of components required to
interface floppy disk drives to a microprocessor system.
Serial Port Interface
The ACC2087 supports two NS16C550 compatible serial ports. Each serial
port interface converts data from peripheral devices or modems from
serial-in-data to parallel-out-data. Data transmitted from the CPU is
converted from parallel-in-data to serial-out-data. The status of the
UART can be read during any CPU operation. Status includes type and
condition of the transfer operations in progress, and error
conditions.
Parallel Port Interface
The parallel port interface in the ACC2087 provides compatibility for
a Centronics type printer. Its configuration register allows the
parallel port to be configured in PS/2 type bi-directional parallel
port and Extended Capabilities Port (ECP) modes.
***Configurations:...
***Features:...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2268 ?486 [no datasheet] ?...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96...
**ACC2020 Power Management Chip c92...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
**
**Other chips...
*ALD...
*ALi...
**M1439/31/45 486 VLB/PCI/ISA [no datasheet, some info] <May95
***Notes:...
***Configurations:...
**M1489/87 FinALi-486 PCI Chipset <Feb95...
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
***Configurations:
M1541/M1542 System Controller
M1533/M1543 PCI-to-ISA Bus Bridge
M1541 + M1533
M1541 + M1543
M1542 + M1533
M1542 + M1543
See the M1531 section for details on the M1533.
The datasheet is very confusing as it does not state how the terms
M1531, M1532, Aladdin V and Aladdin V+ relate to each other. According
to:
http://pclinks.xtreemhost.com/chipsets_pentium.htm
The Aladdin V and Aladdin V+ names are both associated with the M1541.
The M1541 has 5 revisions, A thru E. The M1542 part number is assoc-
iated with revision F onwards. The main difference with the M1542 is
that it now can cache 512MB of RAM, instead of only 128MB. The diff-
erence between the Aladdin V and Aladdin V+ is that the V+ officially
supports a 100 MHz bus, the V only 83.3 MHz.
However, none of this information can be derived from the datasheets
used to write the info and features section.
***Features:...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99
***Notes:...
***Info & Features:...
***Configurations:...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
***PII
None of this information has been checked against actual datasheets.
North/South Name: CPU FSB AGP RAM
M1621/M1533 Aladdin Pro PII 66/100 2x 2GB EDO SDRAM
M1621/M1543/C Aladdin Pro II PII Dual 66/100 2x 2GB EDO SDRAM
M1631/M1535D Aladdin TNT2 (UMA) PIII/Cel 66/100 2x 1.5GB EDO SDRAM
M1632 Aladdin Cyber Blade 2 PIII 100 2x 1.5GB EDO SDRAM
M1641B/M1535D Aladdin Pro 4 PIII/Cel 66/100 4x 1.5GB EDO SDRAM
M1644/M1535D+ Aladdin Cyberblade XT PIII/Cel 100/133 4x 3GB SDRAM DDD
M1644M/M1535D+ Aladdin-T Cyberblade [same as 1644/M1535D+ but supports Tualatin]
M1651/M1535D+ Aladdin Pro 5 PIII/Cel 100/133 4x 3GB SDRAM DDR
M1651T/M1535D+ Aladdin Pro 5T [same as M1651/M1535D+ but supports Tualatin]
"Aladdin Cyberblade" above is short for "CyberAladdin Cyberblade". All
Cyberblade chips have integrated video, as does the Aladdin TNT2.
***Athlon...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86
***Info:...
***Configurations:...
***Features:...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90
assumed to be sx variant of of ELEAT
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88
***Info:...
***Versions:...
***Features:
o Single Chip UART and Analog Data Separator
o 100% functionally compatible to the IBM PS/2 model 50, 60, and 80
o Fully compatible NSl6550 Asynchronous Communications Element
o 16 bytes FIFO for transmitter and receiver buffers
o Easy interface to the Industry standard floppy disk controllers
(765A/765B/8272A)
o Supports multiple data rates (250K, 300K, and 500Kbps)
o High drive, 48 mA output buffer
o Schmitt trigger inputs
o Low power advanced CMOS technology
o 68 pin PLCC or 80 pin Flat Pack
**82C710 Universal Peripheral Controller c:Aug90
***Info:...
***Versions:
82C710
***Features:...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93
***Info:...
***Versions:...
***Features:...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
**66x8 VIA clones [no datasheet] ?
***Notes:...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel
**IBM PC/XT/AT Chip Sets...
**82230/82231 High Integration AT-Compatible Chip Set(ZyMOS) c:Aug88...
**82310 Micro Channel Compatible Peripheral Chip Set 04/21/88...
**82311 High Integration MCA Compatible Perip. Chip Set 11/14/88...
**82320 MCA compatible Chipset [no datasheet] 04/10/89...
**82340DX Chip Set (VLSI) (82346/82345/82355) 01/08/90...
**82340SX Chip Set (VLSI) (82343/82344) 01/25/89...
**82350 EISA Chip Set 07/10/89...
**82350DT EISA Chip Set 04/22/91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82420TX/ZX PCIset (for 486) TX (Saturn), ZX (Saturn II) c:Nov92...
**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
***Configurations:
Parts:
Intel 82434LX (PCMC) PCI/CACHE/MEMORY CONTROLLER
Intel 82433LX (LBX) LOCAL BUS ACCELERATOR
ISA:
82434LX + 2x 82433LX + 82378IB
82434LX + 2x 82433LX + 82378ZB
The main difference between the 82378IB and 82378ZB is the number of
PCI masters supported. See the 82378 section for details.
EISA:
Intel 82434LX + 2x 82433LX + 82374EB + 82375EB
Intel 82434LX + 2x 82433LX + 82374SB + 82375SB
The main difference between the EB and SB variants is that the SB
includes power management options. It was released later when
various enhancements had been made to the EB variant. See the
82374/82375 section for details. It is unlikely the SB variant is
paired with this chipset as it was released when the 430LX was being
replaced with the 430NX.
These chipsets are often paired with the SMC 665 for I/O support or
the NCR 810 for SCSI.
Why this section is so detailed:
Any chips manufactured before Jan 94 have serious problems with the
PCI/EISA bridge's throughput. The problem affects the ISA version too,
but is less pronounced.
Two references from November'93 give some inportant detail that seems
to be missed in the datasheets. It would appear there is an update to
the 82374/82375EB EISA components in late '93, that has some
significant changes. these are not reflected in the datasheets
referenced.
It would appear the mentioned redesign, maps well to the update of
82378 ISA component from the 82378IB to the 82378ZB. Though no
information specifically stating this has been found. It is only that
these are in the same time period.
****References:...
***Features:...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83
***Info:...
***Info:...
***Versions:...
***Features:...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
***Configurations:
82374EB + 82375EB (c93)
82374SB + 82375SB (c94)
***Features:...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
***Features:
o High Performance Second Level Cache
- Zero Wait States at 66 MHz
- Two-Way Set Associative
- Writeback with MESI Protocol
- Concurrent CPU Bus and Memory Bus Operation
- Boundary Scan
o Pentium Processor (735\90, 815\100)
- Chip Set Version of Pentium Processor (735\90, 815\100)
- Superscalar Architecture
- Enhanced Floating Point
- On-Chip 8K Code and 8K Data Caches
- See Pentium Processor Family Data Book for More Information
o Highly Flexible
- 1 Mbyte to 2 Mbyte
- 64-, or 128-Bit Wide Memory Bus
- Synchronous, Asynchronous and Strobed Memory Bus Operation
- Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o Full Multiprocessing Support
- Concurrent CPU, Memory Bus and Snoop Operations
- Complete MESI Protocol
- Internal/External Parity Generation/Checking
- Supports Read For Ownership, Write-Allocation and Cache-to-Cache
Transfers
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
***815p (Solano-3) c:Mar'01
Chips:
[82815P] (MCH) [82801AA] (ICH) [82802] (FWH)
CPUs: P-III/P-III(T)*1/Celeron
DRAM Types: SDRAM PC133
Mem Rows: 6
DRAM Density: 64Mbit 128Mbit 256Mbit
Max Mem: 512MB
ECC/Parity: No
AGP speed: 1x 2x 4x
Bus Speed: 66 100 133
PCI Clock/Bus: 1/2 1/3 1/4 PCI 2.2
>*1 P-III Tualatin first supported from B-0 stepping of chipset.
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
**Notes:...
**GC101/102 12/16MHz PC/AT Compatible Chip Set c:Feb88...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0 c:Jul89...
**GCK113 80386 AT Compatible Chip Set c:oct89...
**GCK181 Universal PS/2 Chip Set c:Mar89...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
***Features:
o Support for 486SX/DX/DX2 CPU
o 2 - 184 pin PQFP devices
o Local bus interface
o 16, 20, 25 and 33MHz CPU speeds
o Fully static operation
o Weitek 4167 supported
o System and Video BIOS on single ROM
o Uses 0.7 Micron HCMOS process
ISA Controller
o AT Compatible
o Synchronized 8MHz ISA bus
o Posted backplane memory writes
o 10 or 16 bit l/O mapping
o Integrated 82375, 82593 and 8254 functionality
o Fast gate A20/Fast reset
Write Buffer
o 4 deep on-chip buffer
o Byte gathering
o Out of order operation
o Full or partial write buffer hits
DRAM Controller
o Line burst capability from DRAM to 80486
o 256K/1M/4M/16M DRAMs
o Mixed memory types
o EMS 4.0
o Hidden refresh operation
o 256MB Maximum system memory
o Staggered refresh
o Shadowing in 16KB increments between 640KB and 1MB
o Remapping
o Fast paging
o 2 or 4 way interleaving
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C360 ISA 386DX Single Chip chipset [no datasheet] ?
***Notes:...
**85C401/402 ISA 486DX/SX Cache chipset [no datasheet] ?...
**85C406/5/411/420/431 EISA 386/486 Chipset [no datasheet] c91...
**85C460 ISA 386DX/486 Single Chip [no datasheet] ?
**85C461 ISA 386DX/486 Single Chip [no datasheet] ?...
**85C471/407 Green PC ISA-VLB 486 Single Chip <94
***Info:...
***Configurations:...
***Features:...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:...
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95
***Info:...
***Configurations:...
***Features:...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96
***Info:...
***Configurations:...
***Features:...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:...
***Configurations:...
***Features:...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?
***Notes:...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:
Each 'LS610 and 'LS612 memory mapper integrated circuit contains a
4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of
2-line to 1-line multiplexers, and other miscellaneous circuitry on a
monolithic chip. Each 'LS610 also contains 12 latches with an enable
control.
The memory mappers are designed to expand a microprocessor's memory
addressing capability by eight bits. Four bits of the memory address
bus (see System Block Diagram)[see datasheet] can be used to select
one of 16 map registers that contain 12 bits each. these 12 bits are
presented to the system memory address bus through the map output
buffers along with the unused memory address bits from the CPU.
However, addressable memory space without reloading the map registers
is the same as would be available with the memory mapper left out.
The addressable memory space is increased only by periodically
reloading the map registers from the data bus. This configuration
lends itself to memory utilization of 16 pages of 2^(n-4) registers
each without reloading (n - number of address bits available from
CPU).
These devices have four modes of operation: read, write, map, and
pass. Data may be read from or loaded into the map register selected
by the register select inputs (RS0 thru RS3) under control of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map operation will output the contents of the map
register selected by the map address inputs (MA0 thru MA3) when CS is
high and MM (map mode control) is low. The 'LS612 output stages are
transparent in this mode, while the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with low levels in the other bit positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
**UM82152 Cache Controller (AUStek A38152 clone) <91
***Info:...
***Versions:...
***Features:...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
***Peripheral:
UM2661 Enhanced Programmable Communications Interface (EPCI)
UM2681 Dual Asynchronous Receiver/Transmitter (DUART)
UM6520/A Peripheral Interface Adapter(PIA) (MC6820)
UM6521/A Peripheral Interface Adapter(PIA) (MC6821)
UM6522/A Versatile Interface Adapter (VIA)
UM6532/A RAM, I/O, Timer Array
UM6551 Asynchronous Communication Interface Adapter (ACIA)
UM82C01 Capacitance Keyboard Encoder (CKE)
UM82C11-C Printer Adapter Interface (PAI)
UM82C450 Asynchronous Communication Element (ACE)
UM82C451 Parallel/Asynchronous Communication Element
UM82C452 Single Chip Multi-I/O (Serial/Parallel)
UM82C550 Asynchronous Communications Element with FIFOs
UM82450 Asynchronous Communication Element (ACE)
UM8250A Asynchronous Communication Element (ACE)
UM8250B Asynchronous Communication Element (ACE)
UM82C8167 RTC
***Other:...
*Unresearched:...
**A - D...
**E - G...
**H - I...
**J - R...
**S...
***Other
Summit chipset - 3/486
Samsung KS82C884
SOLUTIONS 88C211, 88C212, 88C215, P82C206 - isa 386sx c1990
ST Microelectronics PC Client ST86 processor
**T - Z...
***Toshiba ...
***UniChip ...
***USA...
***Other...
*VIA
**SL9XXX FlexSet family General information...
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?
***Info:...
***Versions:...
***Features:...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?
***Info:...
***Versions:...
***Features:...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?
***Info:...
***Versions:...
***Features:...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?
***Info:...
***Versions:...
***Features:...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?
***Notes:...
***Info:
8) The VIA GMC chipset (VIA: 1106/4358) (5/18/96)
--------------------
This chipset includes the VIA VT82C486A-F with a built-in 8042
keyboard controller and a VIA VT82C505-D chipset for the VESA to PCI
bridge. Specifically, the chips are as follows:
82C486A - cache/memory controller + VLB to ISA bridge
82C482 - VLB to ISA bridge (why there are two I'm not sure)
82C483 - DRAM controller
VT82C505 PCI to VLB bridge
A board using this chipset has been unstable (even under DOS/Win), and
did not work with an Adaptec 2940 SCSI controller under OS/2 at all.
Boards based on this chipset are therefore to be avoided. I have,
however, had one report of success from someone using revision G of
this chipset, so it could be that the new revision fixes problems with
older rev's. Designers with whom I've corresponded indicate that
improperly designed boards which use this chipset may have unstable
caches. In addition, the cache controller reads the data into the
cache SRAMs first, then into the CPU, increasing latency and reducing
throughput.
***Configurations:...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97
***Info:...
***Configurations:...
***Features:...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
**Notes:...
**VL82C*** IBM/INTEL Direct replacement ?...
**VL82CPCAT-QC AT 12 MHz 0/1 ws c88...
***Basics:
Max 12MHz "Popular 12 MHz Chip Set"
***Info:
****Overview:...
****VL82C100 ------- PC/AT-Compatible Peripheral Controller...
****VL82C101A/101B - PC/AT-Compatible System Controller...
****VL82C102A ------ PC/AT-Compatible Memory Controller...
****VL82C103/103A -- PC/AT-Compatible Address Buffer...
****VL82C104 - PC/AT-Compatible Data Buffer...
***Configurations:...
***Features:...
**VL82CPCPM-QC AT 16 MHz 0/1 ws [no datasheet] c88...
**VL82CPCAT-16QC/-20QC AT 16 MHz or 20 MHz, 0/1 ws +386SX c89...
**VL82CPCPM-16QC/-20QC AT 16 MHz or 20 MHz, Page-Mode +386SX c89...
**VL82C031/032/033 PS/2 Model 30-compatible chip set c88...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
***Configurations:
VL82C315A-FC
Configurations:
VL82C315A
VL82C315A + VL82C325 (Cache controller)
VL82C315A + VL82C322A (PMU)
VL82C315A + VL82C325 + VL82C322A
Either the VL82C113 or the VL82C114 Combination I/O *should* work with
this chip set.
***Features:...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?
***Info:...
***Versions:...
***Features:...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
***Notes:
from:http://www.cbronline.com/news/vlsi_technology_has_80486sl_notebook_chip_set
The SCAMP IV set comprises three devices - VL82C420 system controller,
VL82C144 peripheral combination chip, and optional VL82C146 ExCA
controller. A standard SCAMP IV system design can be completed with as
few as three TTL components. The devices in the set interconnect via
the VLSI proprietary Multiplexed Local Bus interface; they are
implemented in 0.8 micron CMOS and support mixed voltage operation at
3V and 5V. The VL82C420 is designed to be tightly coupled with the
power-managed Intel CPUs running at up to 33MHz including ones with
clock- doublers. The memory controller supports up to 32Mb.The
peripherals chip also includes floppy disk controller with digital
data separator, a 16C550-compatible universal asynchronous
transmitter-receiver with infra-red support. Power management features
include socket power control, 3.3V/5V suspend with modem and ring
resume detection and power saving with Window inactivity. Up to four
VL82C146s can be used in each system. Samples August, volume October
at $32.50 for the VL82C420, $25.00 for the VL82C144 and $8.50 for the
VL82C146 for 1,000-up.
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?
***Info:...
***Versions:...
***Features:
o High-performance 386DX, 486SX or 486DX interface
o Write buffer - 64 byte (16 DWord)
o External second-level cache - 128 KB
o i486 internal cache control
o BIOS control of second-level cache
o 386SX local bus emulation
o 386SX local bus address pipelining with four word FIFO
o 32-16 bit cycle type translation
o Auto peek cycle operations for both first and second-level cache
o i486 BIOS initialize
o 40 MHz max CPU freq @ 5.0V
33 MHZ max SX freq @ 5.0V
25 MHz max CPU and SX freq @ 3.3V
o Power management plus support for AMD's system Management Mode
(SMM)
o 0.8-micron CMOS technology
o 160-lead metric quad flat pack (MQFP)
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88
***Notes:...
***Info:
****General:...
****FE6000 Enhanced CPU and Peripheral and Control Logic:...
****FE6010 DMA and Channel Control logic:...
****FE6022 Address and Data Buffer Devices:...
****FE6030 Cache/DRAM and Channel Control Device:...
***Configurations:...
***Features:...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
***Info:
GENERAL DESCRIPTION
The WD76C20 is a member of the WD7600 chip set which provides a
cost-effective, power-efficient solution to PC systems design,
especially those relating to "lap-top" devices. The set includes the
WD76C10, the WD76C20, and the WD76C30 as shown in Figure 1-1. Together
these chips provide all necessary logic to build a fully integrated
system board for several varieties of IBM PC/AT compatibles including
systems using 80286, 80386SX, and 80C286 processors.
As part of this chip set, the WD76C20 provides these integral
functions:
o Bus Interface Logic
o IDE Interface
o Chip Select Logic
o Floppy Disk Controller
o Real Time Clock
o Suspend/Resume Logic
The Floppy Disk Controller (FDC) component provides necessary timing
and signalling between the host processor peripheral bus and a floppy
disk drive through a cable connector.
The Real Time Clock component provides calendar and clock information
for the system.
The IDE Interface controls buffering between the system's AT Bus and
PC/AT compatible IDE drive interface.
The Bus Interface Logic controls buffering of data between the
system's AT Bus and the WD76C20.
The Chip Select Logic section provides decoding for selected chip
functions both within the WD76C20 and on the PC/AT motherboard.
Suspend/Resume Logic provides support for chip set power-down and
resume sequences.
***Versions:...
***Features:...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
**W83977EF WINBOND I/O (Multi I/O) <98
***Info:...
***Versions:...
***Features:...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96
***Notes:
Information taken from W83759A datasheet which lists differences to
the W83759. The datasheet is not for the W83759 and W83759A
***Info:...
***Versions:...
***Features:...
**W83769 Local Bus IDE Solution <94
***Info:...
***Versions:...
***Features:...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
*General Sources:...
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