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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:
[no general section in datasheet]
3. Functional Description
3.1 DRAM Controller
3.1.1 DRAM Type
The SiS5571 can support up to 384MBytes (3 banks) of DRAMs and each
bank could be single or double sided 64 bits FP (Fast Page mode) DRAM,
EDO (Extended Data Output) DRAM, and SDRAM (Synchronous DRAM)
DRAM. Half populated bank(32-bit) is also supported.
The installed DRAM type can be 256K, 512k, 1M, 2M, 4M or 16M bit deep
by n bit wide DRAMs, and both symmetrical and asymmetrical type DRAM
are supported. It is also permissible to mix the DRAMs (FP/EDO/SDRAM)
bank by bank and the corresponding DRAM timing will be switched
automatically according to register settings.
3.1.2 DRAM Configuration
The SiS5571 can support single sided or double sided DRAM modules for
each bank. The basic configurations are shown as the following:
3.1.3 Double-sided DRAM [omitted see datasheet]
3.1.4 Single-sided DRAM [omitted see datasheet]
3.1.5 DRAM Scramble Table [omitted see datasheet]
3.1.6 64-bit mapping table [omitted see datasheet]
3.2 DRAM Performance [omitted see datasheet]
3.3 CPU to DRAM Posted Write FIFOs
There is a built-in CPU to Memory posted write buffer with 8 QWord
deep ( CTMFF). All the write access to DRAM will be buffered. For the
CPU read miss / Line fill cycles, the write- back data from the second
level cache will be buffered first, and right after the data had been
posted write into the FIFO, CPU can performs the read operation by the
memory controller starting to read data from DRAMs. The buffered data
are then written to DRAM whenever no any other read DRAM request
comes. With this concurrent write back policy, many wait states are
eliminated. If there comes a bunch of continuous DRAM write cycles,
some ones will be pending if the CTMFF is full.
3.4 32-bit (Half-Populated) DRAM Access
For the read access, there will be either single or burst read cycle
to access the DRAM which depends on the cacheability of the cycle. If
the current DRAM configuration is half-populated bank, then the
SiS5571 will assert 8 consecutive cycles to access DRAM for the burst
cycle. For the single cycle that only accesses DRAM within a DWord,
the SiS5571 will only issue one cycle to access DRAM. For the single
cycle that accesses one Qword or cross DWord boundary, the SiS5571
will issue two consecutive cycles to access DRAM.
3.5 Arbiter
The arbiter is the interface between the DRAM controller and the host
which can access DRAMs. In addition to pass or translate the
information from outside to DRAM controller, arbiter is also
responsible for which master has higher priority to access DRAMs. The
arbiter treats different DRAM access request as DRAM master, and that
makes there be 5 masters which are trying to access DRAMs by sending
their request to the arbiter. After one of them get the grant from the
arbiter, it owns DRAM bus and begins to do memory data transaction.
The masters are: CPU read request, PCI master, Posted write FIFO write
request, and Refresh request. The order of these masters shown above
also stands for their priority to access memory.
3.6 Refresh cycle
The refresh cycle will occur every 15.6 us. It is timed by a counter
of 14Mhz input. The CAS[7:0]# will be asserted at the same time, and
the RAS[5:0]# are asserted sequentially.
3.7 PCI bridge
SiS5571 is able to operate at both asynchronous and synchronous PCI
clocks. Synchronous mode is provided for those synchronous system to
improve the overall system performance. While in the PCI master write
cycles, post-write is always performed. And function of Write Merge
with CPU-to-DRAM post-write buffer is incorporated to eliminate the
penalty of snooping write-back. On the other hand, prefetch is enabled
for master read cycles by default, and such function could be disabled
optionally. And, Direct-Read from CPU-to-DRAM post-write buffer is
implemented to eliminate the overhead of snooping write-back also. In
addition to Write-Merge and Direct-Read, Snoop-Ahead also hides the
overhead of inquiry cycles for master to main memory cycles. These key
functions, Write-Merge, Direct-Read and Snoop-Ahead, achieve the
purpose of zero wait for PCI burst transfer. The post-write and
prefetch buffers are both 16 Double-Word deep FIFOs.
3.8 Snooping Control [omitted see datasheet]
3.9 AHOLD/BOFF# Process and Arbiter Interface [omitted see datasheet]
3.10 Target Initiated Termination [omitted see datasheet]
3.11 DATA Flow [omitted see datasheet]
3.12 PCI Master Read/Write DRAM Cycle [omitted see datasheet]
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM8890 Pentium chipset [no datasheet] ?
***Notes:...
***Configurations:...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97
***Info:...
***Versions:...
***Features:
General
o Plug & Play 1.0A Compliant
o Support 13 IRQs, 4 DMA channels, full 16-bit addresses decoding
o Capable of ISA Bus IRQ Sharing
o Compliant with Microsoft PC97 Hardware Design Guide
o Support DPM (Device Power Management), ACPI
o Programmable configuration settings
o 24 or 14.318 Mhz clock input
FDC
o Compatible with IBM PC AT disk drive systems
o Variable write pre-compensation with track selectable capability
o Support vertical recording format
o DMA enable logic
o 16-byte data FIFOs
o Support floppy disk drives and tape drives
o Detects all overrun and underrun conditions
o Built-in address mark detection circuit to simplify the read
electronics
o FDD anti-virus functions with software write protect and FDD write
enable signal (write data signal was forced to be inactive)
o Support up to four 3.5-inch or 5.25-inch floppy disk drives
o Completely compatible with industry standard 82077
o 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps
data transfer rate
o Support 3-mode FDD, and its Win95 driver
UART
o Two high-speed 16550 compatible UARTs with 16-byte send/receive
FIFOs
o 3rd UART with 32-byte send/receive FIFO is supported for IR
function [W83977AF/AG only]
o MIDI compatible
o Fully programmable serial-interface characteristics:
- 5, 6, 7 or 8-bit characters
- Even, odd or no parity bit generation/detection
- 1, 1.5 or 2 stop bits generation
o Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
o Programmable baud generator allows division of 1.8461 Mhz and
24 Mhz by 1 to (2^16-1)
o Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps
for 24 Mhz
Infrared
o Support IrDA version 1.0 SIR protocol with maximum baud rate up to
115.2K bps
o Support SHARP ASK-IR protocol with maximum baud rate up to 57,600
bps
o Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol
[W83977AF/AG only]
- Single DMA channel for transmitter or receiver
- 3rd UART with 32-byte FIFO is supported in both TX/RX
transmission [W83977AF/AG only]
- 8-byte status FIFO is supported to store received frame status
(such as overrun CRC error, etc.)
o Support auto-config SIR and FIR [W83977AF/AG only]
Parallel Port
o Compatible with IBM parallel port
o Support PS/2 compatible bi-directional parallel port
o Support Enhanced Parallel Port (EPP)
− Compatible with IEEE 1284 specification
o Support Extended Capabilities Port (ECP)
− Compatible with IEEE 1284 specification
o Extension FDD mode supports disk drive B; and Extension 2FDD mode
supports disk drives A and B through parallel port
o Enhanced printer port back-drive current protection
Advanced Power Management (APM) Controlling
o Power turned on when RTC reaches a preset date and time
o Power turned on when a ring pulse or pulse train is detected on the
PHRI, or when a high to low transition on PWAKIN1, or PWAKIN2
input signals
o Power turned on when PANSW input signal indicates a switch on event
o Power turned off when PANSW input signal indicates a switch off
event
o Power turned off when a fail-safe event occurs (power-save mode
detected but system is hung up)
o Power turned off when software issues a power off command
Keyboard Controller
o 8042 based with optional F/W from AMIKKEY-2, Phoenix MultiKey/42 or
customer code
o with 2K bytes of programmable ROM, and 256 bytes of RAM
o Asynchronous Access to Two Data Registers and One status Register
o Software compatibility with the 8042 and PC87911 microcontrollers
o Support PS/2 mouse
o Support port 92
o Support both interrupt and polling modes
o Fast Gate A20 and Hardware Keyboard Reset
o 8 Bit Timer/ Counter; support binary and BCD arithmetic
o 6, 8, 12, or 16 Mhz operating frequency (16 Mhz available only if
input clock rate = 14.318 Mhz)
Real Time Clock
o 27 bytes of clock, On-Now, and control/status register (14 bytes in
Bank 0 and 13 bytes in Bank 2); 242 bytes of general purpose RAM
o BCD or Binary representation of time, calendar, and alarm registers
o Counts seconds, minutes, hours, days of week, days of month, month,
year, and century
o 12-hour/ 24-hour clock with AM/PM in 12-hour mode
o Daylight saving time option; automatic leap-year adjustment
o Dedicated alarm (Alarm B) for On-Now function
o Programmable delay-time between panel switch off and power supply
control
o Software control power-off; various and maskable events to activate
system Power-On
o System Management Interrupt (SMI ) for panel switch power-off event
General Purpose I/O Ports
o 14 programmable general purpose I/O ports; 6 dedicate, 8 optional
o General purpose I/O ports can serve as simple I/O ports, interrupt
steering inputs, watching dog timer output, power LED output,
infrared I/O pins, general purpose address decoder, KBC control I/O
pins.
Package
o 128-pin PQFP
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
*General Sources:...
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