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**CS8221 NEW Enhanced AT (NEAT) (82C211/82C212/82C215/82C206) c86
***Info:
The CS8221 PC/AT compatible NEAT CHIPSet is an enhanced, high
performance 4 chip VLSI implementation (including the 82C206 IPC) of
the control logic used on the IBM Personal Computer AT. The flexible
architecture of the NEAT CHIPSet allows it to be used in any 80286
based system.
The CS8221 NEAT CHIPSet provides a complete 286 PC/AT compatible
system, requiring only 24 logic components plus memory devices.
The CS8221 NEAT CHIPSet consists of the 82C211 CPU/Bus controller, the
82C212 Page/interleave and EMS Memory controller. the 82C215
Data/Address buffer and the 82C206 Integrated Peripherals Controller
(IPC).
The NEAT CHIPSet supports the local CPU bus, a 16 bit system memory
bus, and the AT buses as shown in the NEAT System Block Diagram [see
datasheet]. The 82C211 provides synchronization and control signals
for all buses. The 82C211 also provides an independent AT bus clock
and allows for dynamic selection between the processor clock and the
user selectable AT bus clock. Command delays and wait states are
software configurable, providing flexibility for slow or fast peri-
pheral boards.
The 82C212 Page/interleave and EMS Memory controller provides an
interleaved memory sub-system design with page mode operation. It
supports up to 8 MB of on-board DRAM with combinations of 64Kbit,
256Kbit and 1Mbit DRAMs. The processor can operate at 16MHz with
0.5-0.7 wait state memory accesses, using 100 nsec DRAMs. This is
possible through the Page Interleaved memory scheme. The Shadow RAM
feature allows taster execution of code stored in EPROM, by down
loading code from EPROM to RAM. The RAM then shadows the EPROM for
further code execution. In a DOS environment, memory above 1Mb can be
treated as LIM EMS memory.
The 82C215 Data/Address buffer provides the buffering and latching
between the local CPU address bus and the Peripheral address bus. It
also provides buffering between the local CPU data bus and the memory
data bus. The parity bit generation and error detection logic resides
in the 82C215.
The 82C206 Integrated Peripherals Controller is an integral part of
the NEAT CHIPSet. It is described in the 82C206 Integrated Peri-
pherals Controller data book.
System Overview
The CS8221 NEAT CHIPSet is designed for use in 12 to 16 MHz 80286
based systems and provides complete support for the IBM PC/AT
bus. There are four buses supported by the CS8221 NEAT CHIPSet as
shown in Figure 1 [see datasheet]: CPU local bus (A and D), system
memory bus (MA and MD), I/O channel bus (SA and SD), and X bus (XA and
XD). The system memory bus is used to interface the CPU to the DRAMs
and EPROMs controlled by the 82C212. The I/O channel bus refers to
the bus supporting the AT bus adapters which could be either 8 bit or
16 bit devices. The X bus refers to the peripheral bus to which the
82C206 IPC and other peripherals are attached in an IBM PC/AT.
***Configurations:...
***Features:...
**CS8223 LeAPset [no datasheet] ?
**CS8225 CHIPS/250 PS/2 50/60 [no datasheet, some info] c88...
**CS8227 CHIPSlite (82C235/82C641) ?...
**CS8230 386/AT (82C301/302/303/304/305/306)cFeb87...
**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:...
***Configurations:...
***Features:
o Supports Intel/AMD/Cyrix/IDT Pentium CPU Host Bus at
66/75/83/95/100 MHz and 2.5/3.3V Bus Interface
− Supports the Pipelined Address of Pentium compatible CPU
− Supports the Linear Address Mode of Cyrix CPU
− 100/100, 95/95, 83/83, 75/75 and 66/66 MHz Synchronous
Host/DRAM clocking configuration
− 100/75, 95/75, 83/66, 66/100 and 66/83 MHz Asynchronous
Host/DRAM clocking configuration
− Supports Host Bus operation for integrated 3D VGA Controller
o Meets PC99 Requirements
o Supports PCI Revision 2.2 Specification
o Integrated Super AGP VGA for Hardware 2D/3D Video/Graphics
Accelerators
− Supports tightly coupled 64 bits 100MHz host interface to VGA
to speed up GUI performance and the video playback frame rate
− Built-in programmable 24-bit true-color RAMDAC up to 230 MHz
pixel clock
− Built-in reference voltage generator and monitor sense circuit
− Supports loadable RAMDAC for gamma correction in high color
and true color modes
− Built-in dual-clock generator
− Supports Multiple Adapters and Multiple Monitors
− Built-in PCI multimedia interface
− Flexible design for shared frame buffer or local frame buffer
architecture
− Shared System Memory Area 2MB, 4MB and 8MB
− Supports SDRAM and SGRAM local frame buffer and memory size up
to 8 MB
− Supports Digital Flat Panel Port for Digital Monitor (LCD Panel)
− Supports DVD H/W Accelerator
o Integrated Second Level ( L2 ) Cache Controller
− Write Back Cache Mode
− Direct Mapped Cache Organization
− Supports Pipelined Burst SRAM
− Supports 256K/512K/1M/2M Bytes Cache Sizes
− Cache Hit Read/Write Cycle of 3-1-1-1
− Cache Back-to-Back Read Cycle of 3-1-1-1-1-1-1-1
− Supports Single Read Allocation for L2 Cache
− Supports Concurrency of CPU to L2 cache and Integrated A.G.P.
VGA master to DRAM accesses
o Integrated DRAM Controller
− Supports up to 3 double sided DIMMs (6 rows memory)
− Supports 8Mbytes to 1.5 GBytes of main memory
− Supports Cacheable DRAM Sizes up to 256 MBytes
− Supports 1M/2M/4M/8M/16M/32M x N for 2-bank or 4-bank SDRAM
− Supports 3.3V DRAM
− Supports Concurrent Write Back
− Supports CAS before RAS Refresh, Self Refresh
− Supports Relocation of System Management Memory
− Programmable CS#, DQM#, SRAS#, SCAS#, RAMWE# and MA Driving
Current
− Option to Disable Local Memory in Non-cacheable Regions
− Entries GART cache to Minimize the Number of Memory Bus Cycles
Required for Accessing Graphical Texture Memory
− Programmable Counters to Ensure Guaranteed Minimum Access Time
for Integrated A.G.P. VGA, CPU, and PCI accesses
− Two Programmable Non-cacheable Regions
− Supports X-1-1-1/X-2-2-2 Burst Write Cycles
− Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
− Shadow RAM in Increments of 16 KBytes Built-in 8 Way
Associative/16
− Supports SDRAM 7/8-1-1-1 Burst Read Cycles
o Provides High Performance PCI Arbiter
− Supports up to 4 PCI Masters
− Supports Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead
- Supports Concurrency between CPU to Memory and PCI to PCI
- Supports Concurrency between CPU to 33Mhz PCI Access and 33Mhz
PCI to integrated A.G.P. VGA Access
- Programmable Timers Ensure Guaranteed Minimum Access Time for
PCI Bus Masters, and CPU
o PCI Bus Interface
- Supports 32-bit PCI local bus standard Revision 2.2 compliant
- Integrated write-once subsystem vendor ID configuration register
- Supports zero wait-state memory mapped I/O burst write
- Integrated 2 stages PCI post-write buffer to enhance frame
buffer write performance
- Integrated 256 bits read cache to enhance frame buffer read
performance
- Supports full 16-bit re-locatable VGA I/O address decoding
o Integrated Host-to-PCI Bridge
- Supports Asynchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Zero Wait State Burst Cycles
- Supports Pipelined Process in CPU-to-PCI Access
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Supports Memory Remapping Function for PCI master accessing
Graphical Window
o Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
- Supports Graphic Window Size from 4MBytes to 256MBytes
- Supports Pipelined Process in CPU-to-Integrated 3D A.G.P.
VGA Access
- Supports 8 Way, 16 Entries Page Table Cache for GART to enhance
Integrated A.G.P. VGA Controller Read/Write Performance
- Supports PCI-to-PCI bridge function for memory write from 33Mhz
PCI bus to Integrated A.G.P. VGA
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 12QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer with 2 QW Deep
- PCI-to-Memory Posted Write Buffer with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer with 8 QW Deep
- CPU-to-VGA Posted Write Buffer with 4 QW Deep
o Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for Windows 98 Compliant
Controller
- Plug and Play Compatible
- Supports Scatter and Gather
- Supports Dual Mode Operation - Native Mode and Compatibility
Mode
- Supports IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Supports Multiword DMA Mode 0, 1, 2
- Supports Ultra DMA 33/66
- Two Separate IDE Bus
- Two 16 DW FIFO for PCI Burst Transfers.
o Supports NAND Tree for Ball Connectivity Testing
o 576-Balls BGA Package
o 3.3V Core with mixed 2.5V, 3.3V and 5V I/O CMOS Technology
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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