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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*SIS...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96
***Info:
[no general section in datasheet]

3. Functional Description
3.1 DRAM Controller
3.1.1 DRAM Type
The SiS5571  can support up to  384MBytes (3 banks) of  DRAMs and each
bank could be single or double sided 64 bits FP (Fast Page mode) DRAM,
EDO  (Extended  Data  Output)   DRAM,  and  SDRAM  (Synchronous  DRAM)
DRAM. Half populated bank(32-bit) is also supported.

The installed DRAM type can be 256K,  512k, 1M, 2M, 4M or 16M bit deep
by n bit  wide DRAMs, and both symmetrical  and asymmetrical type DRAM
are supported. It is also  permissible to mix the DRAMs (FP/EDO/SDRAM)
bank  by bank  and  the  corresponding DRAM  timing  will be  switched
automatically according to register settings.

3.1.2 DRAM Configuration

The SiS5571 can support single  sided or double sided DRAM modules for
each bank. The basic configurations are shown as the following:

3.1.3 Double-sided DRAM    [omitted see datasheet]
3.1.4 Single-sided DRAM    [omitted see datasheet]
3.1.5 DRAM Scramble Table  [omitted see datasheet]
3.1.6 64-bit mapping table [omitted see datasheet]

3.2 DRAM Performance       [omitted see datasheet]

3.3 CPU to DRAM Posted Write FIFOs

There is  a built-in CPU  to Memory posted  write buffer with  8 QWord
deep ( CTMFF). All the write  access to DRAM will be buffered. For the
CPU read miss / Line fill cycles, the write- back data from the second
level cache will be buffered first,  and right after the data had been
posted write into the FIFO, CPU can performs the read operation by the
memory controller starting to read  data from DRAMs. The buffered data
are  then written  to DRAM  whenever no  any other  read  DRAM request
comes. With  this concurrent write  back policy, many wait  states are
eliminated. If  there comes a  bunch of continuous DRAM  write cycles,
some ones will be pending if the CTMFF is full.

3.4 32-bit (Half-Populated) DRAM Access
For the read  access, there will be either single  or burst read cycle
to access the DRAM which depends  on the cacheability of the cycle. If
the  current  DRAM  configuration  is half-populated  bank,  then  the
SiS5571 will assert 8 consecutive  cycles to access DRAM for the burst
cycle.  For the  single cycle that only accesses  DRAM within a DWord,
the SiS5571 will  only issue one cycle to access  DRAM. For the single
cycle that  accesses one  Qword or cross  DWord boundary,  the SiS5571
will issue two consecutive cycles to access DRAM.

3.5 Arbiter
The arbiter is the interface  between the DRAM controller and the host
which  can  access  DRAMs.  In  addition  to  pass  or  translate  the
information  from   outside  to  DRAM  controller,   arbiter  is  also
responsible for which master has  higher priority to access DRAMs. The
arbiter treats different DRAM access  request as DRAM master, and that
makes there be  5 masters which are trying to  access DRAMs by sending
their request to the arbiter. After one of them get the grant from the
arbiter, it owns DRAM bus and begins to do memory data transaction.

The masters are: CPU read request, PCI master, Posted write FIFO write
request, and Refresh  request. The order of these  masters shown above
also stands for their priority to access memory.

3.6 Refresh cycle
The refresh cycle  will occur every 15.6 us. It is  timed by a counter
of 14Mhz input.  The CAS[7:0]# will be asserted at  the same time, and
the RAS[5:0]# are asserted sequentially.

3.7 PCI bridge
SiS5571 is  able to operate  at both asynchronous and  synchronous PCI
clocks. Synchronous  mode is provided for those  synchronous system to
improve the overall system performance.  While in the PCI master write
cycles, post-write  is always performed.  And function  of Write Merge
with CPU-to-DRAM  post-write buffer  is incorporated to  eliminate the
penalty of snooping write-back. On the other hand, prefetch is enabled
for master read cycles by default, and such function could be disabled
optionally.  And, Direct-Read  from CPU-to-DRAM  post-write  buffer is
implemented to eliminate the overhead of snooping write-back also.  In
addition to  Write-Merge and  Direct-Read, Snoop-Ahead also  hides the
overhead of inquiry cycles for master to main memory cycles. These key
functions,  Write-Merge,  Direct-Read  and  Snoop-Ahead,  achieve  the
purpose  of zero  wait for  PCI  burst transfer.   The post-write  and
prefetch buffers are both 16 Double-Word deep FIFOs.

3.8  Snooping Control                          [omitted see datasheet]
3.9  AHOLD/BOFF# Process and Arbiter Interface [omitted see datasheet]
3.10 Target Initiated Termination    	       [omitted see datasheet]
3.11 DATA Flow	      			       [omitted see datasheet]
3.12 PCI Master Read/Write DRAM Cycle	       [omitted see datasheet]


***Configurations:...
***Features:
o   Supports Intel Pentium CPU and other compatible CPU at 
    75/66/60/50MHz (external clock speed)
o   Supports the Pipelined Address Mode of Pentium CPU
o   Supports the Full 64-bit Pentium Processor data Bus
o   Supports 32-bit PCI Interface
o   Integrated Second Level (L2) Cache Controller
    - Write Through and Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Integrated 16K bits Dirty Ram
    - Supports Pipelined Burst SRAM
    - Supports 256 KBytes to 512 MBytes Cache Sizes
    - Cache Read/Write Cycle of 3-1-1-1-1-1-1-1 at 66 MHz
o   Integrated DRAM Controller
    - Supports 3 Banks of FP/EDO SIMMs, or 2 Banks of SDRAM DIMMs
    - Supports 2Mbytes to 384Mbytes of main memory
    - Supports 256K/512K/1M/2M/4M/16M x N FP/EDO/SDRAM DRAM
    - Supports 3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Supports 32 bits/64 bits mixed mode configuration
    - Supports Concurrent Write Back for FP/EDO DRAM
    - Supports Mixed DRAM (FP/EDO/SDRAM) Technology
    - Supports CAS before RAS Refresh
    - Supports Relocation of System Management Memory
    - Programmable CAS# ,RAS#, RAMW# and MA Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    - Supports FP DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
    - Supports EDO DRAM 4/5-2-2-2(-2-2-2-2) Burst Read Cycles
    - Supports SDRAM 6/7-1-1-1(-2-1-1-1) Burst Read Cycles
    - Supports X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
    - Supports 8 Qword Deep Buffer for Read/Write Reordering, Dword 
      Merging and 3/2-1-1-1 Post write Cycles
    - Two Programmable Non-Cacheable Regions
    - Option to Disable Local Memory in Non-Cacheable Regions
    - Shadow RAM in Increments of 16 KBytes
o   Integrated PMU Controller
    - Supports SMM Mode of CPU
    - Supports CPU Stop Clock
    - Supports Break Switch
    - Supports Modem Ring Wakeup
    - Supports Automatic Power Supply Control
o   Provides High Performance PCI Arbiter.
    - Supports 3 internal masters and 5 external  PCI Masters
    - Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Supports Concurrency between CPU to Memory and PCI to PCI.
o   Integrated Host-to-PCI Bridge
    - Supports Asynchronous/Synchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles
    - Zero Wait State Burst Cycles
    - Supports 8 DW Deep Buffer for CPU-to-PCI Posted Write Cycles
    - Supports Pipelined Process in CPU-to-PCI Access
    - Supports Advance Snooping for PCI Master Bursting
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Fast back-to-back
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory.
    - CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
    - PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o   Built-in one 32-bit General Purpose Register
o   Integrated PCI-to-ISA Bridge
    - Translates PCI Bus Cycles into ISA Bus Cycles
    - Translates ISA Master or DMA Cycles into PCI Bus Cycles
    - Provides a Dword Post Buffer for PCI to ISA Memory cycles
    - Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master 
      Performance
    - Fully Compliant to PCI 2.1
o   Enhanced DMA Functions
    - 8-, 16- bit DMA Data Transfer
    - ISA compatible, and Fast Type F DMA Cycles
    - Two 8237A Compatible DMA Controllers with Seven Independent 
      Programmable Channels
    - Provides the Readability of the two 8237 Associated Registers
o   Built-in Two 8259A Interrupt Controllers
    - 14 Independently Programmable Channels for Level- or Edge-
      triggered Interrupts
    - Provides the Readability of the two 8259A Associated Registers
o   Three Programmable 16-bit Counters compatible with 8254
    - System Timer Interrupt
    - Generates Refresh Request
    - Speaker Tone Output
    - Provides the Readability of the 8254 Associated Registers
o   Built-in Keyboard Controller
    - Hardwired Logic Provides Instant Response
    - Supports PS/2 Mouse
    - Support Hot Key "Sleep" Function
o   Built-in Real Time Clock(RTC) with 256B CMOS SRAM
o   Fast PCI IDE Master/Slave Controller
    - Fully Compatible with PCI Local Bus Specification V2.1
    - Supports PCI Bus Mastering
    - Plug and Play Compatible
    - Supports Scatter and Gather
    - Supports Dual Mode Operation - Native Mode and 
      Compatibility Mode
    - Supports IDE PIO Timing Mode 0, 1, 2 of ANSI ATA Specification
    - Supports Mode 3 and Mode 4 Timing Proposal on Enhanced IDE 
      Specification
    - Supports Multiword DMA Mode 0, 1, 2
    - Separate IDE Bus
    - Two 8x32-bit FIFO for PCI Burst Read/Write Transfers.
o   Universal Serial Bus Controller
    - Host/Hub Controller
    - Two USB ports
o   On-Board Plug and Play Support
    - One Steerable DMA Channel
    - One Steerable Interrupt
    - One Programmable Chip Select
o   Supports the Reroutibility of the four PCI Interrupts
o   Supports Flash ROM
o   480-Pin BGA Package
o   0.5 μm CMOS Technology

**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
**TACT82411   Snake  Single-Chip AT Controller                     c90
***Notes:...
***Info:...
***Configurations:...
***Features:...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD6400SX/LP   CPU Core Logic for PS/2 386SX Compatibles          <90
***Notes:...
***Info:...
***Configurations:...
***Features:...
**WD6500        CPU Core Logic for PS/2 386DX/486 Compatible       <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX         <11/25/91...
**WD7700/LP     System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855        System controller for 80386SX                <09/25/92...
**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...

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