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M2228 Video
M2301 Video
M2302 Video
M2308 Video
M2401 Video
M3125 Video
M3135 Video (super VGA)
M3143 Video
M3145 PCI Video
M3145 VLB/PCI 3D Video
M3147V PCI Video
M3149 Video
M3151 PCI 3D Video, 4MB MAX
M3307 MPEG Video Decoder Chip
M3309 MPEG-II Video Decoder Chip
M3321 MPEG-II A/V Decoder Chip
M3351 MPEG-II Video Decoder Chip
M4803 PCI EIDE Controller
M5105 VLB Super I/O Controller FDD/HDD/LPT/2xCOM/GAME
M5113 Superset of 5105, with PnP, ECP/EPP LPT and IR port
M5119 Super I/O
M5123 Super I/O PnP/2xCOM/IR port/Keyboard (For Phoenix BIOS)
M5125 same as M5123 but for AMI
M513? Super I/O PnP/Keyboard
M5135F Super I/O PnP/Keyboard/IR
M514? Super I/O PnP/Keyboard/IR/2xCOM/
M5213 PCI IDE
M5217/H Super I/O
M5219 PCI? Bus mastering EIDE
M5225 PCI? EIDE
M5229 PCI? Bus mastering EIDE
M5235 Super I/O
M5237 PCI USB Host
M5240 PCI? EIDE
M5241 PCMCIA Bridge
M5242 ?
M5244 FDD
M5427 PCI-AGP Bridge
M5451 Audio
M5453 Modem
M5455 Audio
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:
o Supports Intel Pentium CPU and other compatible CPU at
75/66/60/50MHz (external clock speed)
o Supports the Pipelined Address Mode of Pentium CPU
o Supports the Full 64-bit Pentium Processor data Bus
o Supports 32-bit PCI Interface
o Integrated Second Level (L2) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty Ram
- Supports Pipelined Burst SRAM
- Supports 256 KBytes to 512 MBytes Cache Sizes
- Cache Read/Write Cycle of 3-1-1-1-1-1-1-1 at 66 MHz
o Integrated DRAM Controller
- Supports 3 Banks of FP/EDO SIMMs, or 2 Banks of SDRAM DIMMs
- Supports 2Mbytes to 384Mbytes of main memory
- Supports 256K/512K/1M/2M/4M/16M x N FP/EDO/SDRAM DRAM
- Supports 3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Supports 32 bits/64 bits mixed mode configuration
- Supports Concurrent Write Back for FP/EDO DRAM
- Supports Mixed DRAM (FP/EDO/SDRAM) Technology
- Supports CAS before RAS Refresh
- Supports Relocation of System Management Memory
- Programmable CAS# ,RAS#, RAMW# and MA Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Supports FP DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
- Supports EDO DRAM 4/5-2-2-2(-2-2-2-2) Burst Read Cycles
- Supports SDRAM 6/7-1-1-1(-2-1-1-1) Burst Read Cycles
- Supports X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Supports 8 Qword Deep Buffer for Read/Write Reordering, Dword
Merging and 3/2-1-1-1 Post write Cycles
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
o Integrated PMU Controller
- Supports SMM Mode of CPU
- Supports CPU Stop Clock
- Supports Break Switch
- Supports Modem Ring Wakeup
- Supports Automatic Power Supply Control
o Provides High Performance PCI Arbiter.
- Supports 3 internal masters and 5 external PCI Masters
- Supports Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Supports Concurrency between CPU to Memory and PCI to PCI.
o Integrated Host-to-PCI Bridge
- Supports Asynchronous/Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles
- Zero Wait State Burst Cycles
- Supports 8 DW Deep Buffer for CPU-to-PCI Posted Write Cycles
- Supports Pipelined Process in CPU-to-PCI Access
- Supports Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Fast back-to-back
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory.
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o Built-in one 32-bit General Purpose Register
o Integrated PCI-to-ISA Bridge
- Translates PCI Bus Cycles into ISA Bus Cycles
- Translates ISA Master or DMA Cycles into PCI Bus Cycles
- Provides a Dword Post Buffer for PCI to ISA Memory cycles
- Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master
Performance
- Fully Compliant to PCI 2.1
o Enhanced DMA Functions
- 8-, 16- bit DMA Data Transfer
- ISA compatible, and Fast Type F DMA Cycles
- Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels
- Provides the Readability of the two 8237 Associated Registers
o Built-in Two 8259A Interrupt Controllers
- 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts
- Provides the Readability of the two 8259A Associated Registers
o Three Programmable 16-bit Counters compatible with 8254
- System Timer Interrupt
- Generates Refresh Request
- Speaker Tone Output
- Provides the Readability of the 8254 Associated Registers
o Built-in Keyboard Controller
- Hardwired Logic Provides Instant Response
- Supports PS/2 Mouse
- Support Hot Key "Sleep" Function
o Built-in Real Time Clock(RTC) with 256B CMOS SRAM
o Fast PCI IDE Master/Slave Controller
- Fully Compatible with PCI Local Bus Specification V2.1
- Supports PCI Bus Mastering
- Plug and Play Compatible
- Supports Scatter and Gather
- Supports Dual Mode Operation - Native Mode and
Compatibility Mode
- Supports IDE PIO Timing Mode 0, 1, 2 of ANSI ATA Specification
- Supports Mode 3 and Mode 4 Timing Proposal on Enhanced IDE
Specification
- Supports Multiword DMA Mode 0, 1, 2
- Separate IDE Bus
- Two 8x32-bit FIFO for PCI Burst Read/Write Transfers.
o Universal Serial Bus Controller
- Host/Hub Controller
- Two USB ports
o On-Board Plug and Play Support
- One Steerable DMA Channel
- One Steerable Interrupt
- One Programmable Chip Select
o Supports the Reroutibility of the four PCI Interrupts
o Supports Flash ROM
o 480-Pin BGA Package
o 0.5 μm CMOS Technology
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82152 Cache Controller (AUStek A38152 clone) <91
***Info:
The UM82152 is a high-performance cache controller for Intel 80386
based systems and provides high levels of integration and
functionality. It interfaces directly to the 80386; no additional
support logic is required. A complete 32-kilobyte cache can be
designed with just one UM82152 and four 8K by 8-bit static RAMs.
The UM82152 architecture enables easy design-in with current speed
versions of the 80386, and simple migration to faster version
processors with no alteration to system or memory design.
The 80386, operating in pipelined mode with the UM82152, runs with
zero wait states during a cache hit (requested data is present in
cache). If the data is not present (cache miss), it is fetched from
main memory by the UM82152. This approach yields the high-speed
performance of fast SRAMs for code and data most frequently used,
while providing design economies (such as board space savings and
lower component costs) by storing infrequently used code and data in
slower dynamic RAM (with cycle times greater than 125 nanoseconds)
that can be located in large memory banks either on-board or
off-board.
The reduced system bus traffic inherent in the UM82152 implementation
produces system performance gains by freeing the bus for use by other
devices.
***Versions:...
***Features:...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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