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*AMD . . . . . . . [no datasheets, some info]...
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*Contaq . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
**SL82C550 'Rossini' Pentium [no datasheet] c:95
***Notes:
from:
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html
The Symphony "Rossini" Chipset (Symphony Labs: 10AD/4269) (9/13/95)
This is apparently a low-cost alternative to the Triton chipset, as it
operates with up to 66 MHz external clock rates, up to two CPUs,
pipelined or non-pipelined, synchronous or [conventional] asynchronous
SRAM cache, EDO RAM, and does dual-port busmastering IDE. It will,
apparently, adjust the voltages to its various (CPU, PCI, cache, RAM)
buses to suit their requirements, and will control up to six PCI
masters. It consists of the SL82C551 cache/memory controller, the
SL82C522 data path controller, and the SL82C555 system I/O controller.
***Configurations:...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**Other:
***VLX*XXX...
***VL16XXX
VL16C450 UART equivalent to VL82C50A but with, scratchpad register, and various improvements
VL16C451 UART equivalent to VL16C450 with Bidirectional Parallel port
VL16C451B 'Enhanced' UART equivalent to VL16C450 with Bidirectional Parallel port
VL16C452 2x UART otherwise equivalent to VL16C451
VL16C452B 'Enhanced'2x UART otherwise equivalent to VL16C451
VL16C550 UART same as VL16C450 but with 16 byte FIFO
VL16C551 UART same as VL16C450 but with 16 byte FIFO (not NSC-compatible?)
VL16C552 UART same as VL16C452 but with 16 byte FIFO
VL16C554 UART same as VL16C552 but Quad
***VL65XXX...
***VL80XXX...
***VL82XXX...
***VL85XXX...
***VL86XXX...
***VXXXXXX...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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