[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96
***Notes:...
***Info:
The OPTi Viper-N+ chipset is the leading solution for PCI-based mobile
applications.   Viper-N+  features   leading  edge   power  management
capability and  flexibility for Intel Pentium  75/90/100/120 and Cyrix
6x86 processor based  notebooks. The chipset incorporates desktop-like
performance features  such as L1 and  L2 cache support,  a full 64-bit
DRAM  controller  and  an  integrated  PCI  controller,  in  a  highly
integrated three chip set.

In  terms of  advanced  power  management, no  chipset  offers a  more
effective, comprehensive or flexible feature set, allowing for maximum
performance  with  minimum  power  consumption  for  extended  battery
life. In  fact, for typical applications,  Viper-N+'s power management
unit reduces power consumption by as much as 80%.

Viper-N+ offers the highest level  of system integration, enabling the
lowest  system  cost  and  real  estate  requirement  for  Pentium-PCI
notebooks.  A system without TTL is achievable with synchronous cache.
And, PCI  offers easy  upgradability to emerging  standard interfaces,
such  as  PCMCIA/CardBus  and  PCI  docking  stations.  Viper-N+  also
features an integrated local bus IDE  controller to avoid ISA data bus
bottlenecks.

OPTi coupled  its expertise in mobile technology  and PCI-based design
to create its second generation  64-bit CPU mobile chipset. The result
is  Viper-N+,  enabling  the  highest levels  of  performance,  system
integration  and  power management  capability  available for  Pentium
PCI-based mobile systems.

***Configurations:...
***Features:...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**Other:
TACT82206  I/O controller (Possibly compatible with C&T 82206)
TACT82300   Not sure if it actually exists.
TACT8230   Not sure if it actually exists.
PCI1050    PCI-to-PC Card Controller
PCI10xx    PCI-to-PC Card16 Controller
PCI1130    PCI-to-PC CardBus Controller
PCI20xx    PCI-to-PCI Bridge

*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C480         System/Cache/ISA bus Controller                   ?
***Info:...
***Configurations:...
***Features:
o   Fully compatible with 486-based ISA bus systems
o   Power-on reset option selects various operational modes
o   Up to 40 MHz CPU operation
o   Replaces the following peripheral logic on the motherboard:
    - Two 82C37A DMA controllers
    - 74LS612 memory mappers (extended to support 64 MB)
    - Two 82C59A interrupt controllers
    - 82C54 timer
    - 82284 clock generator and ready interface
    - 82288 bus controller
o   Memory controller features include:
    - Up to 64 MB system memory
    - 256K, 1M or 4M DRAM
    - Double-sided SIMMs
    - Page Mode DRAM access
    - Two-way interleave support
    - Programmable RAS#/CAS# timing
    - Burst read and write support
    - Parity generation/checking for on-board DRAM
    - Staggered RAS# refresh
o   Supports:
    - One to four banks 32 bits wide
    - 8- or 16-bit wide BIOS ROM
    - shadow RAM in the 640K-1M area
    - Asynchronous ISA bus operation up to 16 MHz
    - Relocation of slot ROMs
    - Access to devices residing on the local bus
    - Weitek 4167 numeric coprocessor
o   0.8-micron CMOS technology
o   208-lead MQFP (metric quad flat pack)
o   Includes:
    - Memory/refresh controller
    - Port A, B, and NMI logic
    - Bus steering logic
    - Turbo control
    - hidden refresh
    - Three-stateable outputs for board testing
o   Selectable slow DRAM refresh saves power
o   On-chip write-back cache controller:
    - External tags
    - Direct map
    - Separate "dirty" RAM not required
    - 2-1-1-1 reads with two banks, 2-2-2-2 with one bank
    - 32 KB to 1MB cache size
    - One wait state writes on cache-hits
    - Optional zero wait state writes
    - Optional one wait state reads
o   Other features:
    - Programmable for 10- or 16-bit internal I/O addressing
    - Programmable drive on the DRAM and ISA bus signals
    - Programmable memory access to define "fast-bus", local bus, slot
      bus, non-cacheable and write-protect areas
    - Input pin defines access to local bus devices

**VL82C481         System/Cache/ISA bus Controller                 c92...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

(c) Copyright mR_Slugs Warehouse - All rights Reserved