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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:
The P5  A.G.P./VGA chipset, SiS530/5595, provides  a high performance/
cost index  Desktop/Mobile solution  for the Intel  Pentium P54C/P55C,
AMD K5/K6/K6-II, Cyrix M1/M2 and  other compatible Pentium CPU with 3D
A.G.P. VGA system.

The Host,  PCI, 3D A.G.P.  Video/Graphics & Memory  Controller, SiS530
integrates the  Host- to-PCI bridge,  the PCI interface, the  L2 cache
controller, the  DRAM controller, the high  performance hardware 2D/3D
VGA controller, and the PCI IDE controller.

The   Host  interface   supports   Synchronous/Asynchronous  Host/DRAM
clocking configuration to eminently improve the system performance and
DRAM compatibility issues.

The L2 cache controller can support up to 2 MB P.B. SRAM, and the DRAM
controller  can support  SDRAM  memory  up to  1.5  GBytes with  three
double-sided  SDRAM  DIMMs  configuration.  The cacheable  DRAM  sizes
support up to 256 MBytes.

The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA33/66 function  that support the data transfer  rate up to 66
MB/s. It provides the separate data path for two IDE channels that can
eminently improve the performance under the multi-tasking environment.

The A.G.P. internal  interface is supported for integrated  H/W 3D VGA
controller. The  integrated VGA controller  is a high  performance and
targeted at  3D graphics application.  In addition,  the integrated 3D
Video/Graphics controller adopts the  64bits 100MHz host bus interface
high  technology  to  improve  the performance  eminently.   To  cost-
effective the PC system, the  share system memory architecture will be
adopted and  it can flexibly using  the 2MB, 4MB and  8MB frame buffer
size  from programming  the system  BIOS. [something  got  confused in
translation  there  didn't it?]  To  enhance  the system  performance,
SiS530 also supports the local  frame buffer solution and memory sizes
can support up to 8MB with SDRAM and SGRAM.

In addition  to provide  the standard interface  for CRT  monitors, it
also  provides  the Digital  Flat  Panel  Port  (DFP) for  a  standard
interface  between  a  personal  computer  and a  digital  flat  panel
monitor. This  port allows a host  computer to connect  directly to an
external  flat panel  monitor without  the need  for analog-to-digital
conversion  found  in most  flat  panel  monitors  today. As  for  DVD
solution,  the  integrated 3D  VGA  controller  also  support DVD  H/W
accelerator to improve the DVD playback performance.

The SiS5595 PCI  system I/O integrates the PCI-to-ISA  bridge with the
DDMA, PC/PCI DMA  and Serial IRQ capability, the  ACPI/Legacy PMU, the
Data  Acquisition   Interface,  the  Universal   Serial  Bus  host/hub
interface,  and the  ISA  bus  interface which  contains  the ISA  bus
controller, the DMA controllers, the interrupt controllers, the Timers
and  the  Real Time  Clock  (RTC).  It  also integrates  the  Keyboard
Controller and PS/2 mouse interface that can support keyboard power on
function  for users  to power  on system  by entering  the hot  key or
password from  keyboard. The built-in  USB controller, which  is fully
compliant to  OHCI (Open Host Controller Interface),  provides two USB
ports  capable  of  running  full/low  speed USB  devices.   The  Data
Acquisition Interface  offers the ability of  monitoring and reporting
the environmental  condition of  the PC. It  could monitor  5 positive
analog voltage inputs, 2 Fan speed inputs, and one temperature input.

In  addition, SiS5595  also supports  ACPI function  to  meet Advanced
Configuration and Power Interface (ACPI) 1.0 specification for Windows
98 environment,  it can support power-management  timer, Power button,
Real-time  clock alarm  wake up,  more  sleeping state,  ACPI LED  for
sleeping and  working state, LAN wake  up, Modem Ring In  wake up, and
OnNow initiative function.

***Configurations:...
***Features:
o   Supports Intel/AMD/Cyrix/IDT Pentium CPU Host Bus at 
    66/75/83/95/100 MHz and 2.5/3.3V Bus Interface
    − Supports the Pipelined Address of Pentium compatible CPU
    − Supports the Linear Address Mode of Cyrix CPU
    − 100/100, 95/95, 83/83, 75/75 and 66/66 MHz Synchronous 
      Host/DRAM clocking configuration
    − 100/75, 95/75, 83/66, 66/100 and 66/83 MHz Asynchronous 
      Host/DRAM clocking configuration
    − Supports Host Bus operation for integrated 3D VGA Controller
o   Meets PC99 Requirements
o   Supports PCI Revision 2.2 Specification
o   Integrated Super AGP VGA for Hardware 2D/3D Video/Graphics 
    Accelerators
    − Supports tightly coupled 64 bits 100MHz host interface to VGA 
      to speed up GUI performance and the video playback frame rate
    − Built-in programmable 24-bit true-color RAMDAC up to 230 MHz 
      pixel clock
    − Built-in reference voltage generator and monitor sense circuit
    − Supports loadable RAMDAC for gamma correction in high color 
      and true color modes
    − Built-in dual-clock generator
    − Supports Multiple Adapters and Multiple Monitors
    − Built-in PCI multimedia interface
    − Flexible design for shared frame buffer or local frame buffer 
      architecture
    − Shared System Memory Area 2MB, 4MB and 8MB
    − Supports SDRAM and SGRAM local frame buffer and memory size up 
      to 8 MB
    − Supports Digital Flat Panel Port for Digital Monitor (LCD Panel)
    − Supports DVD H/W Accelerator
o   Integrated Second Level ( L2 ) Cache Controller
    − Write Back Cache Mode
    − Direct Mapped Cache Organization
    − Supports Pipelined Burst SRAM
    − Supports 256K/512K/1M/2M Bytes Cache Sizes
    − Cache Hit Read/Write Cycle of 3-1-1-1
    − Cache Back-to-Back Read Cycle of 3-1-1-1-1-1-1-1
    − Supports Single Read Allocation for L2 Cache
    − Supports Concurrency of CPU to L2 cache and Integrated A.G.P. 
      VGA master to DRAM accesses
o   Integrated DRAM Controller
    − Supports up to 3 double sided DIMMs (6 rows memory)
    − Supports 8Mbytes to 1.5 GBytes of main memory
    − Supports Cacheable DRAM Sizes up to 256 MBytes
    − Supports 1M/2M/4M/8M/16M/32M x N for 2-bank or 4-bank SDRAM
    − Supports 3.3V DRAM
    − Supports Concurrent Write Back
    − Supports CAS before RAS Refresh, Self Refresh
    − Supports Relocation of System Management Memory
    − Programmable CS#, DQM#, SRAS#, SCAS#, RAMWE# and MA Driving 
      Current
    − Option to Disable Local Memory in Non-cacheable Regions
    − Entries GART cache to Minimize the Number of Memory Bus Cycles 
      Required for Accessing Graphical Texture Memory
    − Programmable Counters to Ensure Guaranteed Minimum Access Time 
      for Integrated A.G.P. VGA, CPU, and PCI accesses
    − Two Programmable Non-cacheable Regions
    − Supports X-1-1-1/X-2-2-2 Burst Write Cycles
    − Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    − Shadow RAM in Increments of 16 KBytes Built-in 8 Way 
      Associative/16
    − Supports SDRAM 7/8-1-1-1 Burst Read Cycles
o   Provides High Performance PCI Arbiter
    − Supports up to 4 PCI Masters
    − Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead
    - Supports Concurrency between CPU to Memory and PCI to PCI
    - Supports Concurrency between CPU to 33Mhz PCI Access and 33Mhz 
      PCI to integrated A.G.P. VGA Access
    - Programmable Timers Ensure Guaranteed Minimum Access Time for 
      PCI Bus Masters, and CPU
o   PCI Bus Interface
    - Supports 32-bit PCI local bus standard Revision 2.2 compliant
    - Integrated write-once subsystem vendor ID configuration register
    - Supports zero wait-state memory mapped I/O burst write
    - Integrated 2 stages PCI post-write buffer to enhance frame 
      buffer write performance
    - Integrated 256 bits read cache to enhance frame buffer read 
      performance
    - Supports full 16-bit re-locatable VGA I/O address decoding
o   Integrated Host-to-PCI Bridge
    - Supports Asynchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Zero Wait State Burst Cycles
    - Supports Pipelined Process in CPU-to-PCI Access
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Supports Memory Remapping Function for PCI master accessing 
      Graphical Window
o   Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
    - Supports Graphic Window Size from 4MBytes to 256MBytes
    - Supports Pipelined Process in CPU-to-Integrated 3D A.G.P. 
      VGA Access
    - Supports 8 Way, 16 Entries Page Table Cache for GART to enhance 
      Integrated A.G.P. VGA Controller Read/Write Performance
    - Supports PCI-to-PCI bridge function for memory write from 33Mhz 
      PCI bus to Integrated A.G.P. VGA
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 12QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory
    - CPU-to-Memory Read Buffer with 4 QW Deep
    - CPU-to-PCI Posted Write Buffer with 2 QW Deep
    - PCI-to-Memory Posted Write Buffer with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer with 8 QW Deep
    - CPU-to-VGA Posted Write Buffer with 4 QW Deep
o   Fast PCI IDE Master/Slave Controller
    - Bus Master Programming Interface for Windows 98 Compliant 
      Controller
    - Plug and Play Compatible
    - Supports Scatter and Gather
    - Supports Dual Mode Operation - Native Mode and Compatibility 
      Mode
    - Supports IDE PIO Timing Mode 0, 1, 2 ,3 and 4
    - Supports Multiword DMA Mode 0, 1, 2
    - Supports Ultra DMA 33/66
    - Two Separate IDE Bus
    - Two 16 DW FIFO for PCI Burst Transfers.
o   Supports NAND Tree for Ball Connectivity Testing
o   576-Balls BGA Package
o   3.3V Core with mixed 2.5V, 3.3V and 5V I/O CMOS Technology

**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C315A/322A/3216  Kodiak 32-Bit Low-Voltage Chip Set            ?
***Info:...
***Configurations:...
**VL82C420/144/146     SCAMP IV [no datasheet, some info]          c93...
**VL82C480         System/Cache/ISA bus Controller                   ?...
**VL82C481         System/Cache/ISA bus Controller                 c92...
**VL82C486         Single-Chip 486, SC486, Controller                ?...
**VL82C425         486 Cache controller                              ?...
**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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