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*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:
o Supports Intel Pentium CPU and other compatible CPU at
75/66/60/50MHz (external clock speed)
o Supports the Pipelined Address Mode of Pentium CPU
o Supports the Full 64-bit Pentium Processor data Bus
o Supports 32-bit PCI Interface
o Integrated Second Level (L2) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty Ram
- Supports Pipelined Burst SRAM
- Supports 256 KBytes to 512 MBytes Cache Sizes
- Cache Read/Write Cycle of 3-1-1-1-1-1-1-1 at 66 MHz
o Integrated DRAM Controller
- Supports 3 Banks of FP/EDO SIMMs, or 2 Banks of SDRAM DIMMs
- Supports 2Mbytes to 384Mbytes of main memory
- Supports 256K/512K/1M/2M/4M/16M x N FP/EDO/SDRAM DRAM
- Supports 3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Supports 32 bits/64 bits mixed mode configuration
- Supports Concurrent Write Back for FP/EDO DRAM
- Supports Mixed DRAM (FP/EDO/SDRAM) Technology
- Supports CAS before RAS Refresh
- Supports Relocation of System Management Memory
- Programmable CAS# ,RAS#, RAMW# and MA Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Supports FP DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
- Supports EDO DRAM 4/5-2-2-2(-2-2-2-2) Burst Read Cycles
- Supports SDRAM 6/7-1-1-1(-2-1-1-1) Burst Read Cycles
- Supports X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Supports 8 Qword Deep Buffer for Read/Write Reordering, Dword
Merging and 3/2-1-1-1 Post write Cycles
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
o Integrated PMU Controller
- Supports SMM Mode of CPU
- Supports CPU Stop Clock
- Supports Break Switch
- Supports Modem Ring Wakeup
- Supports Automatic Power Supply Control
o Provides High Performance PCI Arbiter.
- Supports 3 internal masters and 5 external PCI Masters
- Supports Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Supports Concurrency between CPU to Memory and PCI to PCI.
o Integrated Host-to-PCI Bridge
- Supports Asynchronous/Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles
- Zero Wait State Burst Cycles
- Supports 8 DW Deep Buffer for CPU-to-PCI Posted Write Cycles
- Supports Pipelined Process in CPU-to-PCI Access
- Supports Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Fast back-to-back
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory.
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o Built-in one 32-bit General Purpose Register
o Integrated PCI-to-ISA Bridge
- Translates PCI Bus Cycles into ISA Bus Cycles
- Translates ISA Master or DMA Cycles into PCI Bus Cycles
- Provides a Dword Post Buffer for PCI to ISA Memory cycles
- Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master
Performance
- Fully Compliant to PCI 2.1
o Enhanced DMA Functions
- 8-, 16- bit DMA Data Transfer
- ISA compatible, and Fast Type F DMA Cycles
- Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels
- Provides the Readability of the two 8237 Associated Registers
o Built-in Two 8259A Interrupt Controllers
- 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts
- Provides the Readability of the two 8259A Associated Registers
o Three Programmable 16-bit Counters compatible with 8254
- System Timer Interrupt
- Generates Refresh Request
- Speaker Tone Output
- Provides the Readability of the 8254 Associated Registers
o Built-in Keyboard Controller
- Hardwired Logic Provides Instant Response
- Supports PS/2 Mouse
- Support Hot Key "Sleep" Function
o Built-in Real Time Clock(RTC) with 256B CMOS SRAM
o Fast PCI IDE Master/Slave Controller
- Fully Compatible with PCI Local Bus Specification V2.1
- Supports PCI Bus Mastering
- Plug and Play Compatible
- Supports Scatter and Gather
- Supports Dual Mode Operation - Native Mode and
Compatibility Mode
- Supports IDE PIO Timing Mode 0, 1, 2 of ANSI ATA Specification
- Supports Mode 3 and Mode 4 Timing Proposal on Enhanced IDE
Specification
- Supports Multiword DMA Mode 0, 1, 2
- Separate IDE Bus
- Two 8x32-bit FIFO for PCI Burst Read/Write Transfers.
o Universal Serial Bus Controller
- Host/Hub Controller
- Two USB ports
o On-Board Plug and Play Support
- One Steerable DMA Channel
- One Steerable Interrupt
- One Programmable Chip Select
o Supports the Reroutibility of the four PCI Interrupts
o Supports Flash ROM
o 480-Pin BGA Package
o 0.5 μm CMOS Technology
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro
***Notes (Unverified Information!):...
***5600 c:Nov98...
***600 ?...
***620 c:Apr99...
***621 ?...
***630/630E/S c:Feb00...
***630ST/ET ?...
***633/633T c:Mar01...
***635/635T c:Mar01...
***640T c:Mar01 ...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?
***Info:
The VL82C316 is a true single chip AT, high-performance controller for
386SX-based PC/AT systems. The VL82C316 is intended primarily for low-
power applications requiring a high degree of integration (e.g.
notebooks). However, the VL82C316 is also an excellent choice for
high- integration, low-cost desktop systems running up to 33 MHZ.
The VL82C316 includes the dual 82C37 DMA controllers, dual 82C59A
programmable interrupt controllers, 82C54 programmable interval timer,
82284 clock and ready generator, 82288 bus controller, 8042 keyboard
controller, and 146818A-compatible real-time clock. Also included is
the logic for SMM (system Management Mode) control, address/data bus
control, memory control, shutdown, refresh generation and refresh/DMA
arbitration.
The controller also includes the following:
o AMD and Cyrix compatible SMM and I/O Break interface
o Complete ISA bus interface logic
o Integrated power management features
o Supports slow and self-refresh DRAM
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Optional parity checking logic
o Optional parity generation logic
The VL82C316 supports 387SX-compatible numeric coprocessors including
versions that support slow and stop clock operation.
The memory controller logic is capable of accessing up to 16 MB. There
can be up to four banks of 256K, 1M, or 4M attached in the system or
eight banks of 512K x 8 DRAMS. The VL82C316 can drive the full
compliment of DRAM banks without external buffering. It features
Built-in Page Mode operation. This, along with two-way interleaving
allow the PC designer to maximize system performance using low-cost
DRAMs. Support is also included for zero, one, or two wait state
operation of system DRAM.
Shadowing features are supported on 16k boundaries between C0000h and
DFFFFh, and on 32K boundaries between A0000h and BFFFFh, and between
E0000h and FFFFFh. Simultaneous shadowed ROM, and direct system board
access is possible in a non-overlapping fashion throughout this memory
space. Control over four access options is provided. The options are:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
The VL82C316 handles system board refresh directly and controls the
timing of slot bus refresh. Refresh is performed in the standard
PC/AT-compatible Mode where on- and off-board refreshes are performed
synchronously. Refreshes are staggered to minimize power supply
loading and attenuate noise on the VDD and ground pins. In the
VL82C316, refresh can be programmed to support CAS-before-RAS refresh
operation or standard RAS-only refresh operation, self-refresh, or no
refresh operation. The VL82C316 supports the PC/AT standard refresh
period of 15.625 plus 125 us or 250 us slow refresh options. When the
Suspend Mode is active, the real-time clock's 32 kHz oscillator is
used as the timing reference for absolute minimum power
dissipation. Self-refresh is possible only in the Suspend Mode. DRAM
accesses are not possible in this mode of operation. When
self-refresh is active, it is only enabled when the Suspend Mode is
also active. Otherwise, CAS-before-RAS refresh is used.
A 146818A-compatible real-time clock (RTC) is provided that supports
battery voltages down to 2.4 volt standard. It also includes 128 extra
battery-backed RAM locations (178 total) for operating system and
power-management support. The base address of the RTC is
programmable, but defaults to the PC standard address. the hardware
supports an external RTC. It may be used with the internal RTC or by
itself by disabling the internal RTC.
An internal keyboard controller replaces the standard 8042 required in
a standard PC environment. It provides a keyboard and PS/2 mouse
interface. As an option, the internal keyboard controller can be
disabled allowing use of an external controller.
The 387SX is supported. A software coprocessor reset does not leave a
387SX in the same state as does the reset of a 287. The VL82C316 can
be programmed to disable these software resets if problems arise.
The interrupt controller logic consists of two 82C509A megacells with
eight interrupt request lines each for a total of 16 interrupts. The
two megacells are cascaded internally and two of the interrupt request
inputs are connected to internal circuitry allowing a total of 13
external interrupt requests. There is a special programmable logic
included in the VL82C316 which allows glitch-free inputs on all the
interrupt request pins.
The interval timer includes one 82C54 counter/timer megacell. the
counter/timer has three independent 16-bit counters and six
programmable counter modes.
The DMA controllers are 82C37A compatible. The DMAs control data
transfers bet- ween an I/O channel and on- or off-board memory. DMA
can transfer data over the full 16 MB range available. There are
internal latches provided for latching the middle address bits output
by the 82C37A megacells on the data bus, and 74LS612 memory mappers
are provided to generate the upper address bits. An optional low-
power DMA mode is available. in this mode, the DMA clocks are stopped
except when DMA accesses are in progress.
The VL82C316 can be programmed for asynchronous or synchronous
operation of the AT bus.
The VL82C316 also performs all the data buffer control functions
required. Under the control of the CPU, the VL82C316 chip routes data
to and from the CPU's D bus and the slots (SD bus). The parity is
checked for D bus DRAM read operations. The data is latched for
synchronization with the CPU. Parity OS generated for all data written
to the D bus. The parity function may be optionally disabled except
when 512K x 8 DRAM memory maps are used. In this case, parity is not
an available option.
***Configurations:...
***Features:...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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