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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**55x SoC (System-on-chip) <03/14/02
***Notes:...
***Versions:...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96
***Notes:...
***Info:
The VT82C680 Apollo-P6 is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64 bit Intel
Pentium-Pro super-scalar processors. The chipset supports multi-
Pentium-Pro configuration with Intel GTL+ driver and receiver inter-
face up to 66 MHz external CPU bus speed. The chipset supports the
Pentium-Pro CPU multi-phase bus protocols for split transactions, four
level deep in-order queue and deferred transactions for optimal CPU
throughput.
The VT82C680 chip set consists of the VT82C685 system controller, the
VT82C687 data buffer and the VT82C586 PCI to ISA bridge. The VT82C680
supports six banks of DRAMs up to 1 GB. The DRAM controller supports
Standard Page Mode DRAM, EDO-DRAM, Burst EDO-DRAM and Synchronous DRAM
in a flexible mixed/match manner. The Burst-EDO and Synchronous DRAM
allows zero wait state bursting between the DRAM and the VT82C687 data
buffers at 66 MHz. The six banks of DRAM allow arbitrary mixture of
1M/2M/4M/8M/16MxN DRAMs with optional bank-by-bank ECC and parity
support. The chipset supports sixteen level (quadwords) of CPU to DRAM
write buffers and sixteen level (quadwords) of DRAM to CPU read
buffers to maximize the CPU bus and DRAM utilization. The peak data
transfer rate for the EDO and Synchronous DRAM (or Burst EDO) DRAMs is
266 MB/s and 532 MB/s, respectively.
The VT82C680 supports 3.3/5v 32 bit PCI bus with 64 bit to 32 bit data
conversion. Sixteen levels (doublewords) of post write buffers are
included to allow for concurrent CPU and PCI operation. Consecutive
CPU addresses are converted into burst PCI cycles with Byte merging
capability for optimal CPU to PCI throughput. For PCI master
operation, sixteen levels (doublewords) of post write buffers and
thirty-two levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chipset also supports
enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize
snoop overhead. In addition, the chipset supports advanced features
such as snoop ahead, snoop filtering, CPU write-back forward to PCI
master and CPU write-back merged with PCI post write buffers to
minimize PCI master read latency and DRAM utilization. The VT82C586
PCI to ISA bridge supports four levels (doublewords) of line buffers,
type F DMA transfers and delay transaction to allow efficient PCI bus
utilization (PCI-2.1 compliant). The VT82C586 also includes integrated
keyboard controller with PS2 mouse support, integrated DS12885 style
real time clock with extended 128 Byte CMOS RAM, integrated master
mode enhanced IDE controller with full scatter and gather capability
and extension to 33 MB/sec UltraDMA-33 transfer rate, integrated USB
interface with root hub and two function ports with built-in physical
layer transceiver, and OnNow/ACPI compliant advanced configuration and
power management interface. A complete main board can be implemented
with only six TTLs.
The VT82C680 is ideal for high performance, high quality, high energy
efficient and high integration desktop and notebook PCI/ISA computer
systems.
***Configurations:...
***Features:...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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