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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
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*Unresearched:...
*VIA...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97
***Notes:...
***Info:...
***Configurations:...
***Features:
o AGP / PCI / ISA Mobile and Deep Green PC Ready
- Supports 3.3V and sub-3.3V interface to CPU
- Supports separately powered 3.3V (5V tolerant) interface to
system memory, AGP, and PCI bus
- PC-97 compatible using VIA VT82C586B (208-pin PQFP) south bridge
chip with ACPI Power Management for cost-efficient desktop
applications
- Modular power management and clock control for mobile system
applications
- Combine with VIA VT82C596 (Intel PIIX4 pin compatible 324-pin
BGA) "Mobile South" south bridge chip for state-of-the-art
mobile applications
o High Integration
- Single chip implementation for 64-bit Socket-7-CPU, 64-bit
system memory, 32-bit PCI and 32-bit AGP interfaces
- Apollo MVP3 Chipset: VT82C598MVP system controller and
VT82C586B PCI to ISA bridge
- Chipset includes UltraDMA-33 EIDE, USB, and Keyboard / PS2-Mouse
Interfaces plus RTC / CMOS on chip
o High Performance CPU Interface
- Supports all Socket-7 processors including 64-bit Intel Pentium/
Pentium with MMX, AMD 6k86 (K6), Cyrix/IBM 6x86 / 6x86MX, and
IDT/Centaur C6 CPUs
- 66 / 75 / 83 / 100 MHz CPU external bus speed (internal 300MHz
and above)
- Built-in deskew DLL (Delay Lock Loop) circuitry for optimal skew
control within and between clocking regions
- Cyrix/IBM 6x86 linear burst support
- AMD 6k86 write allocation support
- System management interrupt, memory remap and STPCLK mechanism
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support
- Flexible cache size: 0K / 256K / 512K / 1M / 2MB
- 32 byte line size to match the primary cache
- Integrated 8-bit tag comparator
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access up to
100 MHz
- Tag timing optimized (less than 4ns setup time) to allow
external tag SRAM implementation for most flexible cache
organization
- Sustained 3 cycle write access for PBSRAM access or CPU to
DRAM & PCI bus post write buffers up to 100 MHz
- Supports CPU single read cycle L2 allocation
- System and video BIOS cacheable and write-protect
- Programmable cacheable region
o Full Featured Accelerated Graphics Port (AGP) Controller
- Synchronous and pseudo-synchronous with the host CPU bus with
optimal skew control
PCI AGP CPU DRAM Mode
33MHz 66MHz 100MHz 100MHz 3x synchronous *1
33MHz 66MHz 83MHz 83MHz 2.5x pseudo-synchronous *1
30MHz 60MHz 75MHz 75MHz 2.5x pseudo-synchronous *1
33MHz 66MHz 66MHz 66MHz 2x synchronous *1
33MHz 66MHz 100MHz 66MHz 3x synchronous *2
33MHz 66MHz 83MHz 66MHz 2.5x pseudo-synchronous *2
30MHz 60MHz 75MHz 66MHz 2.5x pseudo-synchronous *2
33MHz 66MHz 66MHz 66MHz 2x synchronous *2
*1 DRAM uses CPU clock, *2 DRAM uses AGP clock
- AGP v2.0 compliant (1x and 2x transfer modes)
- Supports SideBand Addressing (SBA) mode (non-multiplexed
address/data)
- Supports 133MHz 2X mode for AD and SBA signalling
- Pipelined split-transaction long-burst transfers up to 533 MB/
sec
- Eight level read request queue
- Four level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
- Graphics Address Relocation Table (GART)
- One level TLB structure
- Sixteen entry fully associative page table
- LRU replacement scheme
- Independent GART lookup control for host / AGP / PCI master
accesses
- Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport
driver support
o Concurrent PCI Bus Controller
- PCI buses are synchronous / pseudo-synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- 66 MHz PCI operation on the AGP bus
- PCI-to-PCI bridge configuration on the 66MHz PCI bus
- Supports up to five PCI masters
- Peer concurrency
- Concurrent multiple PCI master transactions; i.e., allow PCI
masters from both PCI buses active at the same time
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- PCI master snoop ahead and snoop filtering
- Six levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Forty-eight levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Supports L1/L2 write-back forward to PCI master read to minimize
PCI read latency
- Supports L1/L2 write-back merged with PCI master post-write to
minimize DRAM utilization
- Delay transaction from PCI master reading DRAM
- Read caching for PCI master reading DRAM
- Transaction timer for fair arbitration between PCI masters
(granularity of two PCI clocks)
- Symmetric arbitration between Host/PCI bus for optimized system
performance
- Complete steerable PCI interrupts
- PCI-2.1 compliant, 32 bit 3.3V PCI interface with 5V tolerant
inputs
o Advanced High-Performance DRAM Controller
- DRAM interface synchronous with host CPU (66/75/83/100 MHz) or
AGP (66MHz) for most flexible configuration
- Concurrent CPU and AGP access
- FP, EDO, and SDRAM
- 66MHz and 100MHz (PC100) SDRAM support
- Different DRAM types may be used in mixed combinations
- Different DRAM timing for each bank
- Dynamic Clock Enable (CKE) control for SDRAM power reduction in
mobile and desktop systems
- Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
- 6 banks up to 768MB DRAMs
- Flexible row and column addresses
- 64-bit data width only
- 3.3V DRAM interface with 5V-tolerant inputs
- Programmable I/O drive capability for MA, command, and MD signals
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) or EC (error checking only) for DRAM
integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
- Supports maximum 8-bank interleave (i.e., 8 pages open simultan-
eously); banks are allocated based on LRU
- Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Four quadwords of CPU/cache to DRAM read prefetch buffers
- Concurrent DRAM writeback
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 5-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM
- 6-1-1-1-2-1-1-1 back-to-back accesses for SDRAM
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate and refresh on populated banks only
- CAS before RAS or self refresh
o Mobile System Support
- Independent clock stop controls for CPU / SDRAM, AGP, and PCI
bus
- PCI and AGP bus clock run and clock generator control
- VTT suspend power plane preserves memory data
- Suspend-to-DRAM and Self-Refresh operation
- New VIA BGA VT82C596 “Mobile South” south bridge chip available
soon for support of new mobile features
- Dynamic clock gating for internal functional blocks for power
reduction during normal operation
- Low-leakage I/O pads
o Built-in NAND-tree pin scan test capability
o 3.3V, 0.35um, high speed / low power CMOS process
o 35 x 35 mm, 476 pin BGA Package
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98
***Notes:...
***info:...
***Configurations:...
***Features:
o General
- 492 BGA Package (35mm x 35mm )
- 2.5 Volt +/- 0.2V Core
- Supports separately powered 3.3V tolerant interface to CPU and
Memory
- Supports separately powered 5.0V tolerant interface to PCI bus
and Video interface
- 2.5V, 0.25um, high speed / low power CMOS process
- PC-98/99 compatible using VIA VT82C686A (352-pin BGA) south
bridge chip
- 66 / 100 MHz Operation
CPU Internal DRAM / PCI Comments
AGP VGC
100 MHz 66 MHz 100 MHz 33 MHz synchronous
(DRAM uses CPU clock)
66 MHz 66 MHz 66 MHz 33 MHz synchronous
(DRAM uses CPU clock)
66 MHz 66 MHz 100 MHz 33 MHz Up pseudo-synchronous
(DRAM uses MEM clock)
o Socket 7 Host Interface
- Supports all Socket-7 / Super-7 processors including 64-bit
Intel Pentium / Pentium with MMX , AMD 6K86 (K6 and K6-2),
Cyrix/IBM 6x86 / 6x86MX, IDT/Centaur C6, and Rise MP6 CPUs
- 66 / 100 MHz CPU "Front Side Bus"
- Supports 3.3V and sub-3.3V interface to CPU
- Built-in de-skew PLL (Phase Lock Loop) circuitry for optimal
skew control within and between clocking regions
- Cyrix/IBM 6x86 linear burst support
- AMD K6 and K6-2 write allocation support
- Supports CPU-to-DRAM write combining
- System management interrupt, memory remap and stop clock
mechanisms
o Advanced L2 Cache
- Direct map write-back or write-through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support
- Flexible cache size: 0K / 256K / 512K / 1M / 2MB
- 32 byte line size to match the primary cache
- Integrated 8-bit tag comparator
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM accesses
up to 100 MHz
- Tag timing optimized (less than 4ns setup time) to allow
external tag SRAM implementation for most flexible cache
organization
- Sustained 3 cycle write access for PBSRAM access or CPU to
DRAM & PCI bus post write buffers up to 100 MHz
- Supports CPU single read cycle L2 allocation
- System and video BIOS cacheable and write-protect
- Programmable cacheable region
o Internal Accelerated Graphics Port (AGP) Controller
- AGP v2.0 compliant for 1x and 2x transfer modes
- Pipelined split-transaction long-burst transfers up to
533 MB/sec
- Eight level read request queue
- Four level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
- Graphics Address Relocation Table (GART)
- One level TLB structure
- Sixteen entry fully associative page table
- LRU replacement scheme
- Independent GART lookup control for host / AGP / PCI master
accesses
- Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport
driver support
o Concurrent PCI Bus Controller
- PCI bus is synchronous / pseudo-synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- Supports up to five PCI masters
- Peer concurrency
- Concurrent multiple PCI master transactions; i.e., allow PCI
masters from both PCI buses active at the same time
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- PCI master snoop ahead and snoop filtering
- Six levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Forty-eight levels (double-words) of post write buffers from
PCI masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM
for access by PCI masters
- Supports L1/L2 write-back forward to PCI master read to
minimize PCI read latency
- Supports L1/L2 write-back merged with PCI master post-write to
minimize DRAM utilization
- Delay transaction from PCI master reading DRAM
- Read caching for PCI master reading DRAM
- Transaction timer for fair arbitration between PCI masters
(granularity of two PCI clocks)
- Symmetric arbitration between Host/PCI bus for optimized
system performance
- Complete steerable PCI interrupts
- PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant
inputs
o High-Performance DRAM Controller
- 64-bit DRAM interface synchronous with host CPU (66//100 MHz)
or internal Memory Clock (100 MHz)
- Concurrent CPU and AGP access
- Supports both standard PC100 and "Virtual Channel" PC100
SDRAMs as well as FPG and EDO DRAMs
- Different DRAM types (FPG, EDO, and SDRAM) may be used in
mixed combinations
- Different DRAM timing for each bank
- Dynamic Clock Enable (CKE) control for SDRAM power reduction
- Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
- 6 banks up to 768MB DRAMs
- Flexible row and column addresses
- 64-bit data width only
- 3.3V DRAM interface
- Programmable I/O drive capability for MA, command, and MD
signals
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) or EC (error checking only) for
DRAM integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
- Supports maximum 8-bank interleave (i.e., 8 pages open
simultaneously); banks are allocated based on LRU
- Seamless DRAM command scheduling for maximum DRAM bus
utilization (e.g., precharge other banks while accessing the
current bank)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Four quadwords of CPU/cache to DRAM read prefetch buffers
- Concurrent DRAM writeback
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 5-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM
- 6-1-1-1-2-1-1-1 back-to-back accesses for SDRAM
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate and refresh on populated banks only
- CAS before RAS or self refresh
o Sophisticated Power Management Features
- Independent clock stop controls for CPU / SDRAM, Internal AGP
and PCI bus
- PCI and AGP bus clock run and clock generator control
- Suspend power plane preserves memory data
- Suspend-to-DRAM and Self-Refresh operation
- Dynamic clock gating for internal functional blocks for power
reduction during normal operation
- Low-leakage I/O pads
o General Graphic Capabilities
- 64-bit Single Cycle 2D/3D Graphics Engine
- Supports 2 to 8 Mbytes of Frame Buffer located in System Memory
- Real Time DVD MPEG-2 and AC-3 Playback
- Video Processor
- I2C Serial Interface
- Integrated 24-bit 230MHz True Color DAC
- Extended Screen Resolutions up to 1600x1200
- Extended Text Modes 80 or 132 columns by 25/30/43/60 rows
- DirectX 6 and OpenGL ICD API
o High Performance rCADE3D Accelerator
- 32 entry command queue, 32 entry data queue
- 4Kbyte texture cache with over 90% hit rates
- Pipelined Setup/Texturing/Rendering Engines
- DirectDraw acceleration
- Multiple buffering and page flipping
o Setup Engine
- 32-bit IEEE floating point input data
- Slope and vertex calculations
- Back facing triangle culling
- 1/16 sub-pixel positioning
o Rendering Engine
- High performance single pass execution
- Diffused and specula lighting
- Gouraud and flat shading
- Anti-aliasing including edge, scene, and super-sampling
- OpenGL compliant blending for fog and depth-cueing
- 16-bit Z-buffer
- 8/16/32 bit per pixel color formats
o Texturing Engine
- D3D compressed texture formats DXT1 and DXT2
- Anisotropic texture filtering
- 1/2/4/8-bits per pixel compact palletized textures
- 16/32-bits per pixel quality non-palletized textures
- Pallet formats in ARGB 565, 1555, or 444
- Tri-linear, bi-linear, and point-sampled filtering
- Mip-mapping with multiple Level-Of-Detail (LOD) calculations
and perspective correction
- Color keying for translucency
o 2D GUI Engine
- 8/15/16/24/32-bits per pixel color formats
- 256 Raster Operations (ROPs)
- Accelerated drawing: BitBLTs, lines, polygons, fills,
patterns, clipping, bit masking
- Panning, scrolling, clipping, color expansion, sprites
- 32x32 and 64x64 Hardware Cursor
- DOS graphics and text modes
o DVD
- Hardware-Assisted MPEG-2 Architecture for DVD with AC-3
- Simultaneous motion compensation and front-end processing
(parsing, decryption and decode)
- Supports full DVD 1.0, VCD 2.0 and CD-Karaoke
- Microsoft DirectShow 2.x native support, backward compatible to
MCI
- No additional frame buffer requirements
- Dynamic frame and field de-interlace filtering for high quality
playback on VGA monitors (Bob and Weave)
- Tamper-proof software CSS implementation
- Freeze, Fast-Forward, Slow Motion, Reverse
- Pan-and-Scan support for 16:9 sequence
o Video Processor
- On-chip Color Space Converter (CSC)
- Anti-tearing via two frame buffer based capture surfaces
- Minifier for video stream compression and filtering
- Horizontal/vertical interpolation with edge recovery
- Dual frame buffer apertures for independent memory access for
graphics and video
- YUV 4:2:2/4:1:1/4:2:0 and RGB formats
- Capture / ZV Port to MPEG and video decoder
- Vertical Blank Interval for Intercast
- Overlay differing video and graphic color depths
- Display two simultaneous video streams from both internal AGP
and Capture / ZV Port
- Two scalers and Color Space Converters (CSC) for independent
windows
o Digital Flat Panel (DFP) Interface
- 85MHz DFP interface supports 1024x768 panels
- Allows external TMDS transmitter for advanced panel interfaces
o Testability
- Build-in NAND-tree pin scan test capability
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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