[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
**Other:
82EC100G
82EC800
82EC802G, 82EC802GL - "One Chip32 Bits PC/AT Core Logic"*
82EC810 486
82EC922 Pentium
82EC926 PCI-ISA bridge
>* https://patentimages.storage.googleapis.com/pdfs/US5802555.pdf
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?
***Info:...
***Versions:...
***Features:...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97
***Info:...
***Configurations:...
***Features:
o PCI/ISA Green PC Ready
- Supports 3.3V or 5V interface to CPU, system memory, and / or
PCI bus
- Supports CPUs with internal voltages below 3.3V
- PC-97 compatible using VT82C586B South Bridge with ACPI Power
Management
o High Integration
- Single chip implementation for 64-bit Pentium-CPU, 64-bit system
memory, and 32-bit PCI interface
- VT82C590 Apollo VP2 Chipset: VT82C595 system controller and
VT82C586B PCI to ISA bridge
- Chipset includes UltraDMA-33 EIDE, USB, and Keyboard / PS2-Mouse
Interfaces plus RTC / CMOS on chip
- Six TTLs for a complete main board implementation
o Flexible CPU Interface
- Supports 64-bit Pentium, AMD 5k86 , AMD 6k86 and Cyrix 6x86 CPUs
- CPU external bus speed up to 66 Mhz (internal 200Mhz and above)
- Supports CPU internal write-back cache
- System management interrupt, memory remap and STPCLK mechanism
- Cyrix 6X86 linear burst support
- CPU NA# / Address pipeline capability
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support (with
global write enable feature)
- Flexible cache size: 0K/256K/512K/1M/2MB
- 32 byte line size to match the primary cache
- Integrated 10-bit tag comparator
- 3-1-1-1 read/write timing for PBSRAM access at 66 Mhz
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access at
66 Mhz
- Sustained 3 cycle write access for PBSRAM access or CPU to DRAM
and PCI bus post write buffers at 66 Mhz
- Data streaming for simultaneous primary and secondary cache
line fill
- System and video BIOS cacheable and write-protect
- Programmable cacheable region and cache timing
o Fast DRAM Controller
- Fast Page Mode/EDO/Synchronous-DRAM support in a mixed
combination
- Mixed 1M/2M/4M/8M/16MxN DRAMs
- 6 banks up to 512MB DRAMs
- Flexible row and column addresses
- 64-bit or 32-bit data width in arbitrary mixed combination
- 3.3v and 5v DRAM without external buffers
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) for DRAM integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
(14 MA lines)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Concurrent DRAM writeback
- Speculative DRAM access
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing
for EDO DRAMs at 50/60 MHz
- 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing
for EDO DRAMs at 66 MHz
- 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for
SDRAMs at 66 MHz
- 5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66 MHz
- 6-1-1-1-3-1-1-1 back-to-back access for SDRAM at 66 MHz
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate, CAS-before-RAS refresh and refresh
on populated banks only
o Intelligent PCI Bus Controller
- 32 bit 3.3/5v PCI interface
- Synchronous divide-by-two PCI bus interface
- PCI master snoop ahead and snoop filtering
- PCI master peer concurrency
- Synchronous bus to CPU clock with divide-by-two from the CPU
clock
- Automatic detection of data streaming burst cycles from CPU to
the PCI bus
- Five levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- Forty-eight levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Complete steerable PCI interrupts
- Supports L1 write-back forward to PCI master read to minimize
PCI read latency
- Supports L1 write-back merged with PCI master post-write to
minimize DRAM utilization
- Provides transaction timer to fairly arbitrate between PCI
masters
- PCI-2.1 compliant
o Built-in nand-tree pin scan test capability
o 0.6um mixed voltage, high speed / low power CMOS process
o 328 pin Low-Profile BGA Package
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?
***Info:
The VL82C316 is a true single chip AT, high-performance controller for
386SX-based PC/AT systems. The VL82C316 is intended primarily for low-
power applications requiring a high degree of integration (e.g.
notebooks). However, the VL82C316 is also an excellent choice for
high- integration, low-cost desktop systems running up to 33 MHZ.
The VL82C316 includes the dual 82C37 DMA controllers, dual 82C59A
programmable interrupt controllers, 82C54 programmable interval timer,
82284 clock and ready generator, 82288 bus controller, 8042 keyboard
controller, and 146818A-compatible real-time clock. Also included is
the logic for SMM (system Management Mode) control, address/data bus
control, memory control, shutdown, refresh generation and refresh/DMA
arbitration.
The controller also includes the following:
o AMD and Cyrix compatible SMM and I/O Break interface
o Complete ISA bus interface logic
o Integrated power management features
o Supports slow and self-refresh DRAM
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Optional parity checking logic
o Optional parity generation logic
The VL82C316 supports 387SX-compatible numeric coprocessors including
versions that support slow and stop clock operation.
The memory controller logic is capable of accessing up to 16 MB. There
can be up to four banks of 256K, 1M, or 4M attached in the system or
eight banks of 512K x 8 DRAMS. The VL82C316 can drive the full
compliment of DRAM banks without external buffering. It features
Built-in Page Mode operation. This, along with two-way interleaving
allow the PC designer to maximize system performance using low-cost
DRAMs. Support is also included for zero, one, or two wait state
operation of system DRAM.
Shadowing features are supported on 16k boundaries between C0000h and
DFFFFh, and on 32K boundaries between A0000h and BFFFFh, and between
E0000h and FFFFFh. Simultaneous shadowed ROM, and direct system board
access is possible in a non-overlapping fashion throughout this memory
space. Control over four access options is provided. The options are:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
The VL82C316 handles system board refresh directly and controls the
timing of slot bus refresh. Refresh is performed in the standard
PC/AT-compatible Mode where on- and off-board refreshes are performed
synchronously. Refreshes are staggered to minimize power supply
loading and attenuate noise on the VDD and ground pins. In the
VL82C316, refresh can be programmed to support CAS-before-RAS refresh
operation or standard RAS-only refresh operation, self-refresh, or no
refresh operation. The VL82C316 supports the PC/AT standard refresh
period of 15.625 plus 125 us or 250 us slow refresh options. When the
Suspend Mode is active, the real-time clock's 32 kHz oscillator is
used as the timing reference for absolute minimum power
dissipation. Self-refresh is possible only in the Suspend Mode. DRAM
accesses are not possible in this mode of operation. When
self-refresh is active, it is only enabled when the Suspend Mode is
also active. Otherwise, CAS-before-RAS refresh is used.
A 146818A-compatible real-time clock (RTC) is provided that supports
battery voltages down to 2.4 volt standard. It also includes 128 extra
battery-backed RAM locations (178 total) for operating system and
power-management support. The base address of the RTC is
programmable, but defaults to the PC standard address. the hardware
supports an external RTC. It may be used with the internal RTC or by
itself by disabling the internal RTC.
An internal keyboard controller replaces the standard 8042 required in
a standard PC environment. It provides a keyboard and PS/2 mouse
interface. As an option, the internal keyboard controller can be
disabled allowing use of an external controller.
The 387SX is supported. A software coprocessor reset does not leave a
387SX in the same state as does the reset of a 287. The VL82C316 can
be programmed to disable these software resets if problems arise.
The interrupt controller logic consists of two 82C509A megacells with
eight interrupt request lines each for a total of 16 interrupts. The
two megacells are cascaded internally and two of the interrupt request
inputs are connected to internal circuitry allowing a total of 13
external interrupt requests. There is a special programmable logic
included in the VL82C316 which allows glitch-free inputs on all the
interrupt request pins.
The interval timer includes one 82C54 counter/timer megacell. the
counter/timer has three independent 16-bit counters and six
programmable counter modes.
The DMA controllers are 82C37A compatible. The DMAs control data
transfers bet- ween an I/O channel and on- or off-board memory. DMA
can transfer data over the full 16 MB range available. There are
internal latches provided for latching the middle address bits output
by the 82C37A megacells on the data bus, and 74LS612 memory mappers
are provided to generate the upper address bits. An optional low-
power DMA mode is available. in this mode, the DMA clocks are stopped
except when DMA accesses are in progress.
The VL82C316 can be programmed for asynchronous or synchronous
operation of the AT bus.
The VL82C316 also performs all the data buffer control functions
required. Under the control of the CPU, the VL82C316 chip routes data
to and from the CPU's D bus and the slots (SD bus). The parity is
checked for D bus DRAM read operations. The data is latched for
synchronization with the CPU. Parity OS generated for all data written
to the D bus. The parity function may be optionally disabled except
when 512K x 8 DRAM memory maps are used. In this case, parity is not
an available option.
***Configurations:...
***Features:...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved