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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:
o Supports Intel Pentium CPU and other compatible CPU at
75/66/60/50MHz (external clock speed)
o Supports the Pipelined Address Mode of Pentium CPU
o Supports the Full 64-bit Pentium Processor data Bus
o Supports 32-bit PCI Interface
o Integrated Second Level (L2) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty Ram
- Supports Pipelined Burst SRAM
- Supports 256 KBytes to 512 MBytes Cache Sizes
- Cache Read/Write Cycle of 3-1-1-1-1-1-1-1 at 66 MHz
o Integrated DRAM Controller
- Supports 3 Banks of FP/EDO SIMMs, or 2 Banks of SDRAM DIMMs
- Supports 2Mbytes to 384Mbytes of main memory
- Supports 256K/512K/1M/2M/4M/16M x N FP/EDO/SDRAM DRAM
- Supports 3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Supports 32 bits/64 bits mixed mode configuration
- Supports Concurrent Write Back for FP/EDO DRAM
- Supports Mixed DRAM (FP/EDO/SDRAM) Technology
- Supports CAS before RAS Refresh
- Supports Relocation of System Management Memory
- Programmable CAS# ,RAS#, RAMW# and MA Driving Current
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Supports FP DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
- Supports EDO DRAM 4/5-2-2-2(-2-2-2-2) Burst Read Cycles
- Supports SDRAM 6/7-1-1-1(-2-1-1-1) Burst Read Cycles
- Supports X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Supports 8 Qword Deep Buffer for Read/Write Reordering, Dword
Merging and 3/2-1-1-1 Post write Cycles
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
o Integrated PMU Controller
- Supports SMM Mode of CPU
- Supports CPU Stop Clock
- Supports Break Switch
- Supports Modem Ring Wakeup
- Supports Automatic Power Supply Control
o Provides High Performance PCI Arbiter.
- Supports 3 internal masters and 5 external PCI Masters
- Supports Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Supports Concurrency between CPU to Memory and PCI to PCI.
o Integrated Host-to-PCI Bridge
- Supports Asynchronous/Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles
- Zero Wait State Burst Cycles
- Supports 8 DW Deep Buffer for CPU-to-PCI Posted Write Cycles
- Supports Pipelined Process in CPU-to-PCI Access
- Supports Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
- Fast back-to-back
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always
Sustains 0 Wait Performance on CPU-to-Memory.
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o Built-in one 32-bit General Purpose Register
o Integrated PCI-to-ISA Bridge
- Translates PCI Bus Cycles into ISA Bus Cycles
- Translates ISA Master or DMA Cycles into PCI Bus Cycles
- Provides a Dword Post Buffer for PCI to ISA Memory cycles
- Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master
Performance
- Fully Compliant to PCI 2.1
o Enhanced DMA Functions
- 8-, 16- bit DMA Data Transfer
- ISA compatible, and Fast Type F DMA Cycles
- Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels
- Provides the Readability of the two 8237 Associated Registers
o Built-in Two 8259A Interrupt Controllers
- 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts
- Provides the Readability of the two 8259A Associated Registers
o Three Programmable 16-bit Counters compatible with 8254
- System Timer Interrupt
- Generates Refresh Request
- Speaker Tone Output
- Provides the Readability of the 8254 Associated Registers
o Built-in Keyboard Controller
- Hardwired Logic Provides Instant Response
- Supports PS/2 Mouse
- Support Hot Key "Sleep" Function
o Built-in Real Time Clock(RTC) with 256B CMOS SRAM
o Fast PCI IDE Master/Slave Controller
- Fully Compatible with PCI Local Bus Specification V2.1
- Supports PCI Bus Mastering
- Plug and Play Compatible
- Supports Scatter and Gather
- Supports Dual Mode Operation - Native Mode and
Compatibility Mode
- Supports IDE PIO Timing Mode 0, 1, 2 of ANSI ATA Specification
- Supports Mode 3 and Mode 4 Timing Proposal on Enhanced IDE
Specification
- Supports Multiword DMA Mode 0, 1, 2
- Separate IDE Bus
- Two 8x32-bit FIFO for PCI Burst Read/Write Transfers.
o Universal Serial Bus Controller
- Host/Hub Controller
- Two USB ports
o On-Board Plug and Play Support
- One Steerable DMA Channel
- One Steerable Interrupt
- One Programmable Chip Select
o Supports the Reroutibility of the four PCI Interrupts
o Supports Flash ROM
o 480-Pin BGA Package
o 0.5 μm CMOS Technology
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro
***Notes (Unverified Information!):...
***5600 c:Nov98...
***600 ?...
***620 c:Apr99...
***621 ?...
***630/630E/S c:Feb00...
***630ST/ET ?...
***633/633T c:Mar01...
***635/635T c:Mar01...
***640T c:Mar01 ...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96
***Info:
The VT82C580VP Apollo-VP is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64-bit
P54C/Pentium/K5/M1 super-scalar processors. CPU and cache interface is
supported up to 66Mhz CPU external bus speed (with CPU internal speed
up to 200Mhz and above). The CPU, DRAM and PCI bus are all
independently powered so that each of the bus can be run at 3.3v or
5v, independently. The ISA bus always runs at 5v.
The VT82C580VP chip set consists of the VT82C585VP system controller,
the VT82C586 PCI to ISA bridge, and two instances of the VT82C587VP
data buffers. The CPU bus is minimally loaded with only the CPU,
secondary cache and the chip set. The VT82C587VP data buffers isolate
the CPU bus from the DRAM and PCI bus so that CPU and cache operation
may run reliably at the high frequencies demanded by today's
processors. The VT82C585VP contains arbitration logic to support the
UMA (unified memory architecture) with video/GUI products from major
video vendors. Multiple deep FIFOs (thirty-two double words) are
included between multiple data paths to allow efficient concurrent
operation and DRAM utilization. The VT82C586 PCI to ISA bridge
includes integrated 206-style IPC (DMA, interrupt controller and
timer), integrated keyboard controller with PS2 mouse support,
integrated DS12885 style real time clock with extended 128 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter
and gather capability, and integrated USB (universal serial bus)
interface with root hub and two function ports with built-in physical
layer transceiver. A complete main board can be implemented with only
six TTLs. Please refer to Figure 1 [see datasheet] for the system
block diagram.
***Configurations:...
***Features:...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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