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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:...
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99
***Info:
The SIS950 is a LPC Interface based highly integrated Super I/O. The
SIS950 provides the most commonly used legacy Super I/O functionality
plus the latest Environment Control initiatives, such as Hardware
Monitor, Fan Speed Controller and SiS’s "SmartGuardian" function. The
device’s LPC interface complies with Intel "LPC Interface
Specification Rev. 1.0" (Sept. 29, 1997). The SIS950 meets the
"Microsoft PC98 & PC99 System Design Guide" requirements and is ACPI
compliant.
The SIS950 features the enhanced hardware monitor providing 3 thermal
inputs from remote thermistors, thermal diode or diode-connected
transistor (2N3904). The device also provides the SiS innovative
intelligent automatic Fan ON/OFF & speed control functions
(SmartGuardian) to reduce overall system noise and power consumption.
The SIS950 has integrated nine logical devices, featuring an
Environment Controller (controls three Fans). The Environment
Controller has temperature, voltage and Fan Speed monitors. One Fan
Speed Controller is responsible to control three fan speeds through
three 128 steps of Pulse Width Modulation (PWM) output pins and to
monitor three fan's tachometer inputs.
Other features include one high-performance 2.88MB floppy disk
controller, with digital data separator, supporting two 360K/ 720K/
1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high-performance
parallel port features the bi-directional Standard Parallel Port
(SPP), the Enhanced Parallel Port (EPP V. 1.7 and EPP V. 1.9 are
supported), and the IEEE 1284 compliant Extended Capabilities Port
(ECP). Two 16C550 standard compatible enhanced UARTs perform
asynchronous communication, and support IR, one consumer remote
control (TV remote) IR, one MPU-401 UART mode compatible MIDI port,
one game port with built-in 558 quad timers and buffer chips to
support direct connection of 2 joysticks, and six ports (48 GPIO
pins). There is also a flash ROM interface with Address (FA[0:18]),
Data (FD[0:7]), and supporting three control signals FCS#, FWE# and
FRD#. In addition, a SmartGuardian engine is provided to monitor the
system condition and reacts to the detected condition accordingly.
These nine logical devices can be individually enabled or disabled via
software configuration registers. The SIS950 utilizes power-efficient
circuitry to reduce power consumption. Once a logical device is
disabled, the inputs are gated inhibit, the outputs are TRI-STATE and
the input clock is disabled. The SIS950 requires a single 48/24 MHz
clock input and operates with a single +5V power supply.
The SIS950 is available in 128-pin PQFP (Plastic Quad Flat Package).
***Versions:...
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