[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
**ET9000     "Jaguar" 486 Write Back Cache AT Single Chip       <Jun92
***Info:
The JAGUAR single chip provides high integration and low cost solution
for  a 16,  20, 25,  33  and 50MHz  486/AT based  system design.   Its
flexible architecture  allows Direct Mapped  Cache Implementation with
64KB/128KB/256KB/512KB  Cache.   The JAGUAR  combined  with 82C206  or
compatible peripheral controller offers a 100% PC/AT compatible system
using  less than  12 components  plus memory  devices.  The  ET9000 is
available in the 184-pin Plastic Quad Flatpack package.  The 1.0u high
speed, low power CMOS Technology allows for substantial stability when
running at 33 and 50MHz.

The JAGUAR  includes 486 CPU control,  write[back]-cache control, Page
Mode DRAM Control, a [local] DRAM control, AT Bus Control, Synchronous
AT Bus  Clock Generation, Clock  Switching Logic, data  bus conversion
logic which  performs the conversion  necessary between the 8,  16 and
32-bit  data paths.  A Coprocessor  Interface Logic  to  support Intel
487SX and Weitek 4167 are also included.

The  JAGUAR   ET9000  provides   very  flexible  cache   based  system
implementation  and a  Page Mode  DRAM memory  to  improve performance
during read  miss cycles.  System  performance is further  enhanced by
allowing  Refresh  and CPU  cache  hit  cycles  to occur  concurrently
without holding the CPU during Refresh cycle.

The system  cost is also minimized  by allowing the use  of slow SRAMs
and  DRAMs. The  "Write Back"  cache is  implemented to  minimize DRAM
access time during write cycle.

The JAGUAR is designed to be  100% compatible with the IBM PC/AT. With
its optimized Cache and DRAM design, enhanced features like Shadow RAM
BIOS, and  Concurrent Refresh; a high  performance / low  cost 486/ AT
can be implemented.

***Configurations:...
***Features:
o   100% IBM PC/AT Compatible 1-Chip AT Solution
o   1X clock source
o   Designed to work at 16, 20, 25, 33, and 50MHz for 4868X/486DX 
    system
o   Flexible architecture to support 64KB 128KB, 256KB and 512KB 
    Write Back Cache Subsystems
o   Supports 2-1-1-1, 3-1-1-1, 2-2-2-2, and 3-2-2-2 cache Burst 
    move-in cycles
o   Built-in Comparator
o   Support two programmable non-cacheable regions
o   Up to 64MB DRAM memory support with Page Mode
o   Mixing DRAM configurations 256K, 1M and 4M devices
o   Software Programmable DRAM Wait States
o   Shadow RAM option
o   Support 80487SX and Weitek 4167 Coprocessors
o   Option for write protected, cacheable main and video BIOS
o   Fast Reset and Gate A20 to optimize OS/2
o   Asynchronous and Synchronous AT Bus Clock with programmable 
    clock division options:CLK2 divided by 2, 3, 4, 5, 6, 8, 10
o   Concurrent Refresh and slow refresh supported
o   Support 8Kx8 and 8Kx9 Tag RAM
o   Hardware and Software Turbo Clock Switching
o   Support Local Bus
o   1.0 Micron Low Power, High Speed CMOS Technology
o   Less than 12 components plus memory to implement an 486 
    system
o   184 Pin PQFP package

**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet]       ?...
**82C390SX   "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8       VIA clones [no datasheet]                               ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset                <01/09/95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...