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**82385SX 32-bit Cache Controller for 80386SX 01/25/89
***Notes:...
***Info:
The 82385SX Cache Controller is a high performance peripheral for
Intel's 386 SX Microprocessor. It stores a copy of frequently accessed
code and data from main memory in a zero wait state local cache
memory. The 82385SX allows the 386 SX Microprocessor to run near its
full potential by reducing the average number of CPU wait states to
nearly zero. The dual bus architecture of the 82385SX allows other
masters to access system resources while the 386 SX CPU operates
locally out of its cache. In this situation, the 82385SX's "bus
watching" mechanism preserves cache coherency by monitoring the system
bus address lines at no cost to system or local throughput.
The 82385SX is completely software transparent, protecting the
integrity of system software. High performance and board space savings
are achieved because the 82385SX integrates a cache directory and all
cache management logic on one chip.
1.0 82385SX FUNCTIONAL OVERVIEW
The 82385SX Cache Controller is a high performance peripheral for
Intel's 386 SX microprocessor. This chapter provides an overview of
the 82385SX, and of the basic architecture and operation of a 386 SX
CPU/ 82385SX system.
1.1 82385 OVERVIEW
The main function of a cache memory system is to provide fast local
storage for frequently accessed code and data. The cache system
intercepts 386 SX memory references to see if the required data
resides in the cache. If the data resides in the cache (a hit), it is
returned to the 386 SX without incurring wait states. If the data is
not cached (a miss), the reference is forwarded to the system and the
data retrieved from main memory. An efficient cache will yield a high
"hit rate" (the ratio of cache hits to total 386 SX accesses), such
that the majority of accesses are serviced with zero wait states. The
net effect is that the wait states incurred in a relatively infrequent
miss are averaged over a large number of accesses, resulting in an
average of nearly zero wait states per access. Since cache hits are
serviced locally, a processor operating out of its local cache has a
much lower "bus utilization" which reduces system bus bandwidth
requirements, making more bandwidth available to other bus masters.
The 82385SX Cache Controller integrates a cache directory and all
cache management logic required to support an external 16 Kbyte
cache. The cache directory structure is such that the entire physical
address range of the 386 SX is mapped into the cache. Provision is
made to allow areas of memory to be set aside a non-cacheable. The
user has two cache organization options: direct mapped and 2-way set
associative. Both provide the high hit rates necessary to make a
large, relatively slow main memory array look like a fast, zero wait
state memory to the 386 SX.
A good hit rate is an essential ingredient of a successful cache
implementation. Hit rate is the measure, of how efficient a cache is
in maintaining a copy of the most frequently requested code and data.
However, efficiency is not the only factor for performance
consideration. Just as essential are sound cache management policies.
These policies refer to the handling of 386 SX writes, preservation of
cache coherency, and ease of system design. The 82385SX's "posted
write" capability allows the majority of 386 SX writes, including
non-cacheable, to run with zero wait states, and the 82385SX's "bus
watching" mechanism preserves cache coherency with no impact on system
performance. Physically, the 82385SX ties directly to the 386 SX with
virtually no external logiC.
***Versions:...
***Features:...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:
[no general section in datasheet]
3. Functional Description
3.1 DRAM Controller
3.1.1 DRAM Type
The SiS5571 can support up to 384MBytes (3 banks) of DRAMs and each
bank could be single or double sided 64 bits FP (Fast Page mode) DRAM,
EDO (Extended Data Output) DRAM, and SDRAM (Synchronous DRAM)
DRAM. Half populated bank(32-bit) is also supported.
The installed DRAM type can be 256K, 512k, 1M, 2M, 4M or 16M bit deep
by n bit wide DRAMs, and both symmetrical and asymmetrical type DRAM
are supported. It is also permissible to mix the DRAMs (FP/EDO/SDRAM)
bank by bank and the corresponding DRAM timing will be switched
automatically according to register settings.
3.1.2 DRAM Configuration
The SiS5571 can support single sided or double sided DRAM modules for
each bank. The basic configurations are shown as the following:
3.1.3 Double-sided DRAM [omitted see datasheet]
3.1.4 Single-sided DRAM [omitted see datasheet]
3.1.5 DRAM Scramble Table [omitted see datasheet]
3.1.6 64-bit mapping table [omitted see datasheet]
3.2 DRAM Performance [omitted see datasheet]
3.3 CPU to DRAM Posted Write FIFOs
There is a built-in CPU to Memory posted write buffer with 8 QWord
deep ( CTMFF). All the write access to DRAM will be buffered. For the
CPU read miss / Line fill cycles, the write- back data from the second
level cache will be buffered first, and right after the data had been
posted write into the FIFO, CPU can performs the read operation by the
memory controller starting to read data from DRAMs. The buffered data
are then written to DRAM whenever no any other read DRAM request
comes. With this concurrent write back policy, many wait states are
eliminated. If there comes a bunch of continuous DRAM write cycles,
some ones will be pending if the CTMFF is full.
3.4 32-bit (Half-Populated) DRAM Access
For the read access, there will be either single or burst read cycle
to access the DRAM which depends on the cacheability of the cycle. If
the current DRAM configuration is half-populated bank, then the
SiS5571 will assert 8 consecutive cycles to access DRAM for the burst
cycle. For the single cycle that only accesses DRAM within a DWord,
the SiS5571 will only issue one cycle to access DRAM. For the single
cycle that accesses one Qword or cross DWord boundary, the SiS5571
will issue two consecutive cycles to access DRAM.
3.5 Arbiter
The arbiter is the interface between the DRAM controller and the host
which can access DRAMs. In addition to pass or translate the
information from outside to DRAM controller, arbiter is also
responsible for which master has higher priority to access DRAMs. The
arbiter treats different DRAM access request as DRAM master, and that
makes there be 5 masters which are trying to access DRAMs by sending
their request to the arbiter. After one of them get the grant from the
arbiter, it owns DRAM bus and begins to do memory data transaction.
The masters are: CPU read request, PCI master, Posted write FIFO write
request, and Refresh request. The order of these masters shown above
also stands for their priority to access memory.
3.6 Refresh cycle
The refresh cycle will occur every 15.6 us. It is timed by a counter
of 14Mhz input. The CAS[7:0]# will be asserted at the same time, and
the RAS[5:0]# are asserted sequentially.
3.7 PCI bridge
SiS5571 is able to operate at both asynchronous and synchronous PCI
clocks. Synchronous mode is provided for those synchronous system to
improve the overall system performance. While in the PCI master write
cycles, post-write is always performed. And function of Write Merge
with CPU-to-DRAM post-write buffer is incorporated to eliminate the
penalty of snooping write-back. On the other hand, prefetch is enabled
for master read cycles by default, and such function could be disabled
optionally. And, Direct-Read from CPU-to-DRAM post-write buffer is
implemented to eliminate the overhead of snooping write-back also. In
addition to Write-Merge and Direct-Read, Snoop-Ahead also hides the
overhead of inquiry cycles for master to main memory cycles. These key
functions, Write-Merge, Direct-Read and Snoop-Ahead, achieve the
purpose of zero wait for PCI burst transfer. The post-write and
prefetch buffers are both 16 Double-Word deep FIFOs.
3.8 Snooping Control [omitted see datasheet]
3.9 AHOLD/BOFF# Process and Arbiter Interface [omitted see datasheet]
3.10 Target Initiated Termination [omitted see datasheet]
3.11 DATA Flow [omitted see datasheet]
3.12 PCI Master Read/Write DRAM Cycle [omitted see datasheet]
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro
***Notes (Unverified Information!):...
***5600 c:Nov98...
***600 ?...
***620 c:Apr99...
***621 ?...
***630/630E/S c:Feb00...
***630ST/ET ?...
***633/633T c:Mar01...
***635/635T c:Mar01...
***640T c:Mar01 ...
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