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**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97
***Notes:...
***Info:
The Intel 380FB PCIset (380FB) consists of the 82380FB Mobile
PCI-to-PCI Bridge (MPCI2) and the 82380AB Mobile PCI-to-ISA Bridge
(MISA). The 380FB supports four PCI slots and three ISA slots. The
MPCI2 and MISA can also be used individually to provide either PCI
slot expansion or ISA slot expansion.
The 380FB supports a full Hot Docking capable docking station with 5V
PCI and ISA add-in expansion slots. MPCI2 provides the docking con-
trol for hot insertion, power management, and a PCI-to-PCI bridge to a
5V PCI desktop style add-in bus. Internal arbitration supports four
bus masters on the secondary PCI bus. The PC/PCI arbitration interface
logic provides PC/PCI bridge support. The 380FB controls all docking,
undocking and suspend/resume sequences for the docking station. The
EPROM interface logic provides an industry standard interface to a
non-volatile memory device (EPROM) for supporting dynamic
autoconfiguration of a previously configured notebook/docking station
combination. The Power management logic provides a control and status
interface between the docking station and notebook that allows the
docking station to control the state of the notebook. A non-volatile
memory interface is used to store docking identification and notebook
configuration information to speed dynamic configuration for a
pre-configured notebook docking combination.
MPCI2 supports the PCI bus enumeration mechanism for PCI-to-PCI
bridges. This is needed to support the Windows 95 dynamic
configuration of system resources when the system docks or
undocks. Otherwise, the operating system must reset the system after
reconfiguration. The undocking mechanism of the 380FB guarantees a
safe notebook removal. Event notification allows docking resources to
be dynamically removed and applications gracefully shut down, if
needed. A hardware mechanism is provided to indicate when the notebook
is prepared to undock. This can be used to eject or unlock the
notebook from the docking station.
The MPCI2’s subtractive decoding guarantees that all accesses targeted
for a downstream ISA bridge (such as the MISA) arrive at their
destination. Software does not need to determine the devices on the
ISA bridge and then program positive decode ranges (as is needed on
traditional positive decode bridges).
***Versions:...
***Features:...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C088 PC/XT Integration Chip <91
***Info:...
***Configurations:...
***Features:
o Fully IBM-PC/XT compatible
o 82C84 Clock generator with 2 clock-inputs to generate the CPU
clock. These are 14.318 MHz and 30 MHz which will support 4.77 MHz
and 10 MHz CPU clocks with 1/3 duty cycle.
o 82C88 Bus Controller
o 82C37 4 channel DMA controller, channel is used for DRAM refresh
o 82C59 8 channel interrupt controller, level is used for system
time base, and level 1 for keyboard input
o 82C53 3 channel timer, channel is used for system time base,
channel 1 for DRAM refresh, and channel 2 for speaker audio
o 82C55 Peripheral l/O r used for keyboard interface and system
configuration switch (same as the PC/XT)
o 74322 Keyboard interface, supports PC/XT type keyboard
o 74280 Parity check and generator
o 74670 4 bit page register for DMA
o Wait state logic
o NMI control logic
o ROM decoder for one 2764 and one 27256
o RAM decoder for 4164 or 41256 DRAM
o H/W and S/W CPU speed change and indicator
o Built-in delay line for RAS, CAS
o Low power consumption: less than 300 mW at 10 MHz CPU speed
o Small PCB size: 100 pin plastic Flat package
**UM82C230 286AT MORTAR Chip Set <91...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94
***Notes:...
***Configurations:...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
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*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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