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*_IBM...
*ACC Micro...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88
***Info:
The ACC 5500 is a multifunction chip designed for motherboards or
add-in cards compatible with IBM PS/2 Model 50/60 systems. The ACC
5500 has an NS 16450 compatible asynchronous communications element to
build a serial port and a bidirectional parallel port interface that
supports a Centronics type printer and allows the parallel port to
receive data from external devices. The ACC 5500 uses an external
signal input as the input clock source.
***Versions:...
***Features:...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89
***Notes:...
***Info:
The 82385SX Cache Controller is a high performance peripheral for
Intel's 386 SX Microprocessor. It stores a copy of frequently accessed
code and data from main memory in a zero wait state local cache
memory. The 82385SX allows the 386 SX Microprocessor to run near its
full potential by reducing the average number of CPU wait states to
nearly zero. The dual bus architecture of the 82385SX allows other
masters to access system resources while the 386 SX CPU operates
locally out of its cache. In this situation, the 82385SX's "bus
watching" mechanism preserves cache coherency by monitoring the system
bus address lines at no cost to system or local throughput.
The 82385SX is completely software transparent, protecting the
integrity of system software. High performance and board space savings
are achieved because the 82385SX integrates a cache directory and all
cache management logic on one chip.
1.0 82385SX FUNCTIONAL OVERVIEW
The 82385SX Cache Controller is a high performance peripheral for
Intel's 386 SX microprocessor. This chapter provides an overview of
the 82385SX, and of the basic architecture and operation of a 386 SX
CPU/ 82385SX system.
1.1 82385 OVERVIEW
The main function of a cache memory system is to provide fast local
storage for frequently accessed code and data. The cache system
intercepts 386 SX memory references to see if the required data
resides in the cache. If the data resides in the cache (a hit), it is
returned to the 386 SX without incurring wait states. If the data is
not cached (a miss), the reference is forwarded to the system and the
data retrieved from main memory. An efficient cache will yield a high
"hit rate" (the ratio of cache hits to total 386 SX accesses), such
that the majority of accesses are serviced with zero wait states. The
net effect is that the wait states incurred in a relatively infrequent
miss are averaged over a large number of accesses, resulting in an
average of nearly zero wait states per access. Since cache hits are
serviced locally, a processor operating out of its local cache has a
much lower "bus utilization" which reduces system bus bandwidth
requirements, making more bandwidth available to other bus masters.
The 82385SX Cache Controller integrates a cache directory and all
cache management logic required to support an external 16 Kbyte
cache. The cache directory structure is such that the entire physical
address range of the 386 SX is mapped into the cache. Provision is
made to allow areas of memory to be set aside a non-cacheable. The
user has two cache organization options: direct mapped and 2-way set
associative. Both provide the high hit rates necessary to make a
large, relatively slow main memory array look like a fast, zero wait
state memory to the 386 SX.
A good hit rate is an essential ingredient of a successful cache
implementation. Hit rate is the measure, of how efficient a cache is
in maintaining a copy of the most frequently requested code and data.
However, efficiency is not the only factor for performance
consideration. Just as essential are sound cache management policies.
These policies refer to the handling of 386 SX writes, preservation of
cache coherency, and ease of system design. The 82385SX's "posted
write" capability allows the majority of 386 SX writes, including
non-cacheable, to run with zero wait states, and the 82385SX's "bus
watching" mechanism preserves cache coherency with no impact on system
performance. Physically, the 82385SX ties directly to the 386 SX with
virtually no external logiC.
***Versions:...
***Features:...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97
***Info:...
***Configuration:...
***Features:...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97
***Info:...
***Versions:...
***Features:...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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