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**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94
***Notes:...
***Info:
The 82420EX PCIset is the foundation for the Value Flexible
Motherboard solution for entry-level Intel486 processor-based PCI
systems. The Value Flexible Motherboard solution, including 82420EX,
Intel486 processor, 82091AA Advanced Integrated Peripherals, 82C42
Keyboard Controller, Flash BIOS, and Plug & Play software, drives PCI
into the mainstream. The 82420EX PCIset is a highly integrated
solution enabling low cost, small form factor motherboard designs. All
Intel486 processors and upgrades are supported, including L1
write-back and Intel SMM power management. PCI Local Bus IDE is
incorporated for higher performance IDE at no additional cost.
The 82420EX was designed from the ground up for PCI performance. It
consists of two components - the 82425EX PCI System Controller (PSC)
and the 82426EX ISA Bridge (IB). The PSC integrates the L2 cache
controller and the DRAM controller. The cache controller supports both
write-through and write-back cache policies and cache sizes from 64
KBytes to 512 KBytes in an interleaved or non-interleaved
configuration. The DRAM controller interfaces main memory to the Host
Bus and the PCI Bus. The PSC supports a two-way interleaved DRAM
organization for optimum performance. Up to ten single-sided SIMMs or
four double-sided and two single-sided SIMMs provide a maximum of 128
MBytes of main memory. The PSC provides memory write posting to PCI
for enhanced CPU-to-PCI memory write performance. In addition, the PSC
provides a high performance PCI Local Bus IDE interface.
The IB is the bridge between the ISA Bus and Host Bus, and integrates
the common I/O functions found in today’s ISA-based PC systems - a
seven channel DMA controller, two 82C59 interrupt controllers, an 8254
timer/counter, Intel SMM power management support, and control logic
for NMI generation. The IB also provides the decode for external BIOS,
real time clock, and keyboard controller. Edge/Level interrupts and
interrupt steering are supported for PCI plug and play compatibility.
The IB integrates the ISA address and data path, reducing TTL and
system cost. In addition, the integration of system clock generation
logic eliminates the need for external host and PCI clock drivers.
***Configurations:...
***Features:...
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96
***Info:
[no general section in datasheet]
3. Functional Description
3.1 DRAM Controller
3.1.1 DRAM Type
The SiS5571 can support up to 384MBytes (3 banks) of DRAMs and each
bank could be single or double sided 64 bits FP (Fast Page mode) DRAM,
EDO (Extended Data Output) DRAM, and SDRAM (Synchronous DRAM)
DRAM. Half populated bank(32-bit) is also supported.
The installed DRAM type can be 256K, 512k, 1M, 2M, 4M or 16M bit deep
by n bit wide DRAMs, and both symmetrical and asymmetrical type DRAM
are supported. It is also permissible to mix the DRAMs (FP/EDO/SDRAM)
bank by bank and the corresponding DRAM timing will be switched
automatically according to register settings.
3.1.2 DRAM Configuration
The SiS5571 can support single sided or double sided DRAM modules for
each bank. The basic configurations are shown as the following:
3.1.3 Double-sided DRAM [omitted see datasheet]
3.1.4 Single-sided DRAM [omitted see datasheet]
3.1.5 DRAM Scramble Table [omitted see datasheet]
3.1.6 64-bit mapping table [omitted see datasheet]
3.2 DRAM Performance [omitted see datasheet]
3.3 CPU to DRAM Posted Write FIFOs
There is a built-in CPU to Memory posted write buffer with 8 QWord
deep ( CTMFF). All the write access to DRAM will be buffered. For the
CPU read miss / Line fill cycles, the write- back data from the second
level cache will be buffered first, and right after the data had been
posted write into the FIFO, CPU can performs the read operation by the
memory controller starting to read data from DRAMs. The buffered data
are then written to DRAM whenever no any other read DRAM request
comes. With this concurrent write back policy, many wait states are
eliminated. If there comes a bunch of continuous DRAM write cycles,
some ones will be pending if the CTMFF is full.
3.4 32-bit (Half-Populated) DRAM Access
For the read access, there will be either single or burst read cycle
to access the DRAM which depends on the cacheability of the cycle. If
the current DRAM configuration is half-populated bank, then the
SiS5571 will assert 8 consecutive cycles to access DRAM for the burst
cycle. For the single cycle that only accesses DRAM within a DWord,
the SiS5571 will only issue one cycle to access DRAM. For the single
cycle that accesses one Qword or cross DWord boundary, the SiS5571
will issue two consecutive cycles to access DRAM.
3.5 Arbiter
The arbiter is the interface between the DRAM controller and the host
which can access DRAMs. In addition to pass or translate the
information from outside to DRAM controller, arbiter is also
responsible for which master has higher priority to access DRAMs. The
arbiter treats different DRAM access request as DRAM master, and that
makes there be 5 masters which are trying to access DRAMs by sending
their request to the arbiter. After one of them get the grant from the
arbiter, it owns DRAM bus and begins to do memory data transaction.
The masters are: CPU read request, PCI master, Posted write FIFO write
request, and Refresh request. The order of these masters shown above
also stands for their priority to access memory.
3.6 Refresh cycle
The refresh cycle will occur every 15.6 us. It is timed by a counter
of 14Mhz input. The CAS[7:0]# will be asserted at the same time, and
the RAS[5:0]# are asserted sequentially.
3.7 PCI bridge
SiS5571 is able to operate at both asynchronous and synchronous PCI
clocks. Synchronous mode is provided for those synchronous system to
improve the overall system performance. While in the PCI master write
cycles, post-write is always performed. And function of Write Merge
with CPU-to-DRAM post-write buffer is incorporated to eliminate the
penalty of snooping write-back. On the other hand, prefetch is enabled
for master read cycles by default, and such function could be disabled
optionally. And, Direct-Read from CPU-to-DRAM post-write buffer is
implemented to eliminate the overhead of snooping write-back also. In
addition to Write-Merge and Direct-Read, Snoop-Ahead also hides the
overhead of inquiry cycles for master to main memory cycles. These key
functions, Write-Merge, Direct-Read and Snoop-Ahead, achieve the
purpose of zero wait for PCI burst transfer. The post-write and
prefetch buffers are both 16 Double-Word deep FIFOs.
3.8 Snooping Control [omitted see datasheet]
3.9 AHOLD/BOFF# Process and Arbiter Interface [omitted see datasheet]
3.10 Target Initiated Termination [omitted see datasheet]
3.11 DATA Flow [omitted see datasheet]
3.12 PCI Master Read/Write DRAM Cycle [omitted see datasheet]
***Configurations:...
***Features:...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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