[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
**ACC2086    486 VL-based System Super Chip Soluti[no datasheet]     ?
***Notes:
Full title:486 VL-based System Super Chip Solution

Info sourced from:http://www.accmicro.com/guide.html
https://web-beta.archive.org/web/19980201100152/http://www.accmicro.com:80/guide.html
 
***Info:...
***Configurations:...
**ACC2087    Enhanced Super Chip (486 Single Chip)              <Aug96...
**ACC2089    486 PCI-based System Super Chip      [no datasheet]     ?...
**ACC2168/GT 32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2178A   32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2268    ?486                                 [no datasheet]     ?...
**ACC????    Maple/Maple-133 486-System-On-Chip   [no datasheet]     ?...
**
**Support Chips:
**ACC2016    Buffer and MUX Logic                                  c96...
**ACC2020    Power Management Chip                                 c92...
**ACC5500    Multifunction I/O Control Chip for PS2 Model 50/60    c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89
***Notes:...
***Info:...
***Versions:...
***Features:...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97
***Info:...
***Configuration:...
***Features:
o   Support Intel Pentium CPU and other compatible CPU host bus at 
    50/55/60/66/75 MHz
o   Support CPU with MMX feature
o   Support the Pipelined Address Mode of Pentium CPU
o   Support the Full 64-bit Pentium Processor data Bus
o   Meet PC97 Requirements
o   Integrated Second Level (L2) Cache Controller
    - Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Integrated 16K bits Dirty RAM
    - Support Pipelined Burst SRAM
    - Support 256 KBytes and 512 KBytes Cache Sizes
    - Cache Hit Read/Write Cycle of 3-1-1-1
    - Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
o   Integrated DRAM Controller
    - Support 6 RAS Line (3 Banks) of FPM/EDO/SDRAM DIMMs/SIMMs
    - Support 2Mbytes to 384Mbytes of main memory
    - Support Cacheable DRAM Sizes up to 128 MBytes.
    - Support 256K/512K/1M/2M/4M/8M/16M/32M x N FPM/EDO/SDRAM DRAM
    - Support 64 Mb DRAM Technology
    - Support 3.3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Support 32 bits/64 bits mixed mode configuration
    - Support Concurrent Write Back
    - Support CAS before RAS Refresh
    - Support Relocation of System Management Memory
    - Programmable CAS#, RAS#, RAMWE# and MA Driving Current.
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    - Support FPM DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
    - Support EDO DRAM 5-2-2-2(-2-2-2-2) Burst Read Cycles
    - Support SDRAM 6-1-1-1(-2-1-1-1) Burst Read Cycles
    - Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
    - Support 8 Qword Deep Buffer for Read/Write Reordering, Dword 
      Merging and 3/2-1-1-1 Post write Cycles
    - Two Programmable Non-Cacheable Regions
    - Option to Disable Local Memory in Non-Cacheable Regions
    - Shadow RAM in Increments of 16 KBytes
o   Integrated PMU Controller
    - Meet ACPI Requirements
    - Support Both ACPI and Legacy PMU
    - Support Suspend to Disk
    - Support SMM Mode of CPU
    - Support CPU Stop Clock
    - Support Power Button for ACPI function
    - Support Automatic Power Control for system power off function
    - Support Modem Ring-in, RTC Alarm Wake up
    - Support Thermal Detection
    - Support GPIOs, and GPOs for External Devices Control
    - Support Programmable Chip Select
o   Provides High Performance PCI Arbiter.
    - Support up to 5 PCI Masters
    - Support Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Support Concurrency between CPU to Memory and PCI to PCI
o   Integrated Host-to-PCI Bridge
    - Support Asynchronous and Synchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles
    - Zero Wait State Burst Cycles
    - Support IDE Posted Write
    - Support Pipelined Process in CPU-to-PCI Access
    - Support Advance Snooping for PCI Master Bursting
    - Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, 
      Always Sustains 0 Wait Performance on CPU-to-Memory.
    - CPU-to-Memory Read Buffer with 4 QW Deep
    - CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
    - PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, 
      Always Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o   Integrated PCI-to-ISA Bridge
    - Translates PCI Bus Cycles into ISA Bus Cycles
    - Translates ISA Master or DMA Cycles into PCI Bus Cycles
    - Provides a Dword Post Buffer for PCI to ISA Memory cycles
    - Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master 
      Performance
    - Fully Compliant to PCI 2.1
o   Enhanced DMA Functions
    - 8-, 16- bit DMA Data Transfer
    - ISA compatible, and Fast Type F DMA Cycles
    - Two 8237A Compatible DMA Controllers with Seven Independent 
      Programmable Channels
    - Provides the Readability of the two 8237 Associated Registers
    - Support Distributed DMA
o   Built-in Two 8259A Interrupt Controllers
    - 14 Independently Programmable Channels for Level- or Edge-
      triggered Interrupts
    - Provides the Readability of the two 8259A Associated Registers
    - Support Serial IRQ
o   Three Programmable 16-bit Counters compatible with 8254
    - System Timer Interrupt
    - Generates Refresh Request
    - Speaker Tone Output
    - Provides the Readability of the 8254 Associated Registers
o   Built-in Keyboard Controller
    - Hardwired Logic Provides Instant Response
    - Support PS/2 Mouse interface
    - Support Hot Key "Wake-up" Function
    - Capable of Enable/Disable Internal KBC and PS2 Mouse
o   Built-in Real Time Clock(RTC) with 256B CMOS SRAM
    - Built-in up to one Month Alarm for ACPI
o   Fast PCI IDE Master/Slave Controller
    - Bus Master Programming Interface for ATA Windows 95 Compliant 
      Controller
    - Support PCI Bus Mastering
    - Plug and Play Compatible
    - Support Scatter and Gather
    - Support Dual Mode Operation - Native Mode and Compatibility 
      Mode
    - Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
    - Support Multiword DMA Mode 0, 1, 2
    - Support Ultra DMA/33
    - Two Separate IDE Bus
    - Two 16 Dword FIFO for PCI Burst Transfers.
o   Universal Serial Bus Host Controller
    - OpenHCI Host Controller with Root Hub
    - Two USB ports
    - Support Over Current Detection
    - Support Legacy Devices
o   Support I2C serial Bus
o   Support the Reroutibility of the four PCI Interrupts
o   Support 2Mb Flash ROM Interface
o   Support NAND Tree for ball connectivity testing
o   553-Balls BGA Package
o   0.35μm 3.3V Technology   

**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97
***Info:...
***Versions:...
***Features:...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

(c) Copyright mR_Slugs Warehouse - All rights Reserved