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**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor to form a CPU Cache chip set designed for high
performance servers and function-rich desktops. The high speed
interconnect between the CPU and cache components has been optimized
to provide zero-wait state operation. This CPU Cache chip set is
fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82496 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit wide memory bus widths, 16, 32, and 64 byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82491, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91
***Notes:
InfoWorld Oct 28, 1991 p38:
"...Unlike earlier EISA chip sets, Ti's Tact84500 is comprised of only
four VLSI chips for controlling the bus, memory, peripherals, and data
path unit. The Tact unit can also control eight EISA bus masters along
with DRAM and a single-layer EISA-bus write buffer. According to TI,
the suggested price of the EISA chip set, at $130 in quantities of
100, should make EISA-based systems price competitive with existing
ISA-based systems."
At least one of the chips is called 84542. This is probably the memory
controller.
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