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**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?
***Info:...
***Configurations:...
***Features:...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
**ET2000 386/486 WB Chipset ?
***Info:...
***Configurations:...
***Features:
o Process technology used 0.8u CMOS
o CPUs supported Intel 80486, 80486SX, AMD Am386DX Am486DX, Cyrix
486DLC
o CPU speed supported 16/20/25/33/40/50 MHZ
o CPU speed supported in 386 system (No external PALS required)
Intel 80387/ Cyrix / HT/ULSI / WEITEK 3167
o Coprocessors supported in 486 system (No external PALS required)
WEITEK 4167
o AT clock generation Async / Sync
o Programmable AT bus clock Yes
o Hardware / Software turbo switching Yes
o Page Mode DRAM control Yes
o Double word interleave control Yes
o DRAM type supported 256K/1M/4M/16M
o Mixing DRAMS Yes
o Concurrent and AT Refresh Yes
o Shadow RAM range maximum size / block size 256 KB / 64KB
o Support EISA/ ISA bus compatibility Yes
o Support Local Bus Yes
o PQFP package: ETISP - 184, ETCMC, ETEBC, ETEDB -l60
o Maximum Physical DRAM 256MB
o Programmable wait states Yes
o On chip cache controller Yes
o Support 8kx8 and 8kx9 Tag RAM Yes
o Cache update scheme Write back
o Cache organization Direct mapped
o Data cache size 32KB-1 MB
o Non-cacheable support Yes
o Each non-cacheable region size 512KB-32MB
o Zero wait state cache read hit Yes
o Zero wait state cache write hit Yes
o SRAM Burst mode support 2-1-1-1, 2-2-2-2, 3-1-1-1, 3-2-2-2 Yes
o DRAM Burst mode support Yes
o External TTL component 11 - 13
o SRAM speed required @ 50MHz 20ns
o SRAM speed required @ 40MHZ 20ns
o SRAM speed required @ 33MHz 20ns
o SRAM speed required @ 25MHz 35ns
o AENx generator Yes
o Fast gate A20 Yes
o Fast reset Yes
**ET6000 "Cheetah" 486DX/SX Non-Cache System <Apr92...
**ET9000 "Jaguar" 486 Write Back Cache AT Single Chip <Jun92...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet] ?...
**82C390SX "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8 VIA clones [no datasheet] ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor (735\90, 810\100) to form a CPU Cache chip set
designed for high performance servers and function-rich desktops. The
high-speed interconnect between the CPU and cache components has been
optimized to provide zero-wait state operation. This CPU Cache chip
set is fully compatible with existing software, and has new data
integrity features for mission critical applications.
The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82497 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82492 is a customized high-performance SRAM that supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82492, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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