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**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
**ET2000     386/486 WB Chipset                                      ?
***Info:...
***Configurations:
ET2000
***Features:
o   Process technology used 0.8u CMOS
o   CPUs supported Intel 80486, 80486SX, AMD Am386DX Am486DX, Cyrix 
    486DLC
o   CPU speed supported 16/20/25/33/40/50 MHZ
o   CPU speed supported in 386 system (No external PALS required)
    Intel 80387/ Cyrix / HT/ULSI / WEITEK 3167
o   Coprocessors supported in 486 system (No external PALS required) 
    WEITEK 4167
o   AT clock generation Async / Sync
o   Programmable AT bus clock Yes
o   Hardware / Software turbo switching Yes
o   Page Mode DRAM control Yes
o   Double word interleave control Yes
o   DRAM type supported 256K/1M/4M/16M
o   Mixing DRAMS Yes
o   Concurrent and AT Refresh Yes
o   Shadow RAM range maximum size / block size  256 KB / 64KB
o   Support EISA/ ISA bus compatibility Yes
o   Support Local Bus Yes
o   PQFP package: ETISP - 184, ETCMC, ETEBC, ETEDB -l60
o   Maximum Physical DRAM 256MB
o   Programmable wait states Yes
o   On chip cache controller Yes
o   Support 8kx8 and 8kx9 Tag RAM Yes
o   Cache update scheme Write back
o   Cache organization Direct mapped
o   Data cache size 32KB-1 MB
o   Non-cacheable support Yes
o   Each non-cacheable region size 512KB-32MB
o   Zero wait state cache read hit Yes
o   Zero wait state cache write hit Yes
o   SRAM Burst mode support 2-1-1-1, 2-2-2-2, 3-1-1-1, 3-2-2-2 Yes
o   DRAM Burst mode support Yes
o   External TTL component 11 - 13
o   SRAM speed required @ 50MHz 20ns
o   SRAM speed required @ 40MHZ 20ns
o   SRAM speed required @ 33MHz 20ns
o   SRAM speed required @ 25MHz 35ns
o   AENx generator Yes
o   Fast gate A20 Yes
o   Fast reset Yes

**ET6000     "Cheetah" 486DX/SX Non-Cache System                <Apr92...
**ET9000     "Jaguar" 486 Write Back Cache AT Single Chip       <Jun92...
**ET9800/391 "Firefox" 386SX Write Back chipset [no datasheet]       ?...
**82C390SX   "Panda" S.C. 386SX Direct Mapped Cache [no d.sheet]cFeb92...
**66x8       VIA clones [no datasheet]                               ?...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...