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N93N8042/A CHIPS AT Keyboard Controller

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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:
o   Two-Way, Set Associative, Secondary Cache for i860 XP 
    Microprocessor
o   50 MHz "No Glue" Interface with CPU
o   Configurable
    - Cache Size 256 or 512 Kbytes
    - Line Width 32, 64 or 128 Bytes
    - Memory Bus Width 64 or 128 Bits
o   Dual-Ported Structure Permits Simultaneous Operations on CPU and
    Memory Buses
o   Efficient MRU Way Prediction
    - Zero Wait States on MRU Hit
    - One Walt State on MRU Miss
o   Dynamically Selectable Update Policies
    - Write-Through
    - Write-Once
    - Write-Back
o   MESI Cache Consistency Protocol
o   Hardware Cache Snooping
o   Maintains Consistency with Primary Cache via Inclusion Principle
o   Flexible User-Implemented Memory Interface Enables Wide Range of
    Product Differentiation
    - Clocked or Strobed
    - Synchronous or Asynchronous
    - Plpelining
    - Memory Bus Protocol
o   82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid 
    Array Package
o   82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack 
    Package

**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**82c801         SCWB2 DX Single Chip Solution                    c:92
***Notes:...
***Info:
The  82C801  SCWB2  can  be  summarized in  four  words:  integration,
performance,  features  and  reliability.   The  best  value  for  the
OEM/system house.

The SCWB2 is  the result of an engineering team driven  by the need to
provide  the fastest, most  reliable solutions  in the  smallest, most
cost effective package and having complete confidence in compatibility
and reliability of the product. With a feature set that doesn't take a
back seat to any solution in the market.

From the 50  MHz Write back Cache to complete  local bus support, this
chip is  everything a  system designer needs  to provide  his customer
with state-of-the-art solutions for high performance PCs in the market
today - and for some time to come.

The  SCWB2 is designed  for the  OEM/system house  who needs  a single
chip, local  bus, lightning performance, design  flexibility, 8 banks,
quick-to-market, and cost effectiveness.


***Configurations:...
***Features:...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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