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**82C721   Universal Peripheral Controller III                 c:May93
***Info:
The CHIPS  82C721 enhanced I/O peripheral controller  is a single-chip
solution  offering  complete  I/O  capabilities for  PC/AT  and  PC/XT
environments.  The  82C721   supports  motherboard  applications  with
configuration via software.

The  82C721  features  a   floppy  disk  controller,  a  digital  data
separator, two 16450 compatible UARTs, a bi-directional parallel port,
an IDE interface control logic and a game port chip select.

The floppy  disk controller is software compatible  with NEC uPD72065B
floppy  disk controller.  The  controller supports  up to  four drives
directly. The digital data separator is capable of data transfer rates
up to 500kb/sec and requires no external components.

The 82C721 has two UARTs  which are compatible with NS16450 UARTs. The
IDE control logic provides a  complete IDE interface for embedded hard
disk  drives.  The  bidirectional  parallel  port  maintains  complete
compatibility with ISA and PS/2  parallel ports.  It can be configured
for either output mode or for bidirectional mode.

The  configuration   RAM  and  circuitry   support  programmable  base
addresses for  all the registers. Selection of  sources of interrupts,
enabling and configuring of on-chip  subsystems and the control of the
configuration  process itself  are also  handled by  this RAM  and its
associated circuitry.  The game port chip select provides a predefined
I/O address decode for games and joy stick applications.

The 82C721,  designed for  motherboard applications, is  provided with
several  power  management features,  which  are controllable  through
hardware  or  software. In  hardware,  the  device  can be  completely
powered down through  a power-down pin.  In this  mode, all inputs are
disabled, all outputs are inactive,  and the contents of all registers
are  preserved  (as long  as  the  power  supply is  maintained).   In
software,   the  device   allows  each   port  to   be   powered  down
independently.

The  82C721 features 24mA  drivers for  output buffers,  including the
host  data bus  and  the parallel  port  data bus.  The floppy  output
drivers  are  capable  of  sinking  48mA. The  host  interface  is  PC
compatible and can be connected directly to the ISA bus.

***Versions:...
***Features:...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93
***Info:
The F87000  Multi-Mode Peripheral  Chip is a  companion to  the F8680A
PC/CHIP single-chip PC. By strapping  pins to select the desired mode,
the F87000 device becomes one of four integrated peripheral chips that
extend the functionality of PC/CHIP.

Chips and Technologies, Inc. has designed the F87000 chip specifically
for use  with the F8680A  microchip to accommodate  portable computing
devices   and  embedded   control   applications  where   integration,
conservation of board space, and power consumption are critical.

In  PCMCIA  card  implementations,  card buffering  and  isolation  is
recommended for  design robustness,  especially in rugged  use enviro-
nments.  The buffering ensures that  the PCMCIA card receives a strong
clean  signal, while the  isolation provides  both the  protection for
"hot card insertion" and is hardwired for turning off power to a card.
Hardware isolation,  supported with Power  Management SuperState code,
minimizes the system’s power  consumption.  PCMCIA card slots that are
not properly buffered and isolated run  a high risk of a system crash/
failure if the cards are inserted/removed while the slot is powered.

The PC/CHIP F87000 is designed to be used in four modes. 
o    Mode 1 ---- Single PCMCIA card buffering support provides:
     • 20-bit address buffer.
     • 16-bit bidirectional data buffer.
     • Buffering for five control signals.
o    Modes 2 and 3 ---- Dual PCMCIA card buffering support provides:
     • Individual address buffering (64MB each).
     • Individual data bus buffering.
     • Two OR gates.
o    Mode 4 ---- Multifunctional mode provides:
     • Keyboard circuitry interfacing to a 16 x 8 keyboard matrix.
     • Clock divider conversion of 14.31818MHz to 1.8432MHz output 
       (divide by 7.77).
     • Parallel printer port.
     • IDE interface.
     • 7-bit configuration ports plus external select for port 
       expansion.

***Versions:...
***Features:...
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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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