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**82C721 Universal Peripheral Controller III c:May93
***Info:
The CHIPS 82C721 enhanced I/O peripheral controller is a single-chip
solution offering complete I/O capabilities for PC/AT and PC/XT
environments. The 82C721 supports motherboard applications with
configuration via software.
The 82C721 features a floppy disk controller, a digital data
separator, two 16450 compatible UARTs, a bi-directional parallel port,
an IDE interface control logic and a game port chip select.
The floppy disk controller is software compatible with NEC uPD72065B
floppy disk controller. The controller supports up to four drives
directly. The digital data separator is capable of data transfer rates
up to 500kb/sec and requires no external components.
The 82C721 has two UARTs which are compatible with NS16450 UARTs. The
IDE control logic provides a complete IDE interface for embedded hard
disk drives. The bidirectional parallel port maintains complete
compatibility with ISA and PS/2 parallel ports. It can be configured
for either output mode or for bidirectional mode.
The configuration RAM and circuitry support programmable base
addresses for all the registers. Selection of sources of interrupts,
enabling and configuring of on-chip subsystems and the control of the
configuration process itself are also handled by this RAM and its
associated circuitry. The game port chip select provides a predefined
I/O address decode for games and joy stick applications.
The 82C721, designed for motherboard applications, is provided with
several power management features, which are controllable through
hardware or software. In hardware, the device can be completely
powered down through a power-down pin. In this mode, all inputs are
disabled, all outputs are inactive, and the contents of all registers
are preserved (as long as the power supply is maintained). In
software, the device allows each port to be powered down
independently.
The 82C721 features 24mA drivers for output buffers, including the
host data bus and the parallel port data bus. The floppy output
drivers are capable of sinking 48mA. The host interface is PC
compatible and can be connected directly to the ISA bus.
***Versions:...
***Features:...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93
***Info:...
***Versions:...
***Features:
o Fully static design substantially reduces power consumption when
compared to discrete TTL designs, allowing direct battery drive.
o 3.3V or 5V operation provides flexibility for system design and
allows dynamic 3.3/5V switching of system voltage to further
reduce power consumption.
o Each F8700 device can be strapped to configure one of three
buffer modes or a multi-function mode, reducing parts inventory
requirements.
o High integration means each F8700 mode replaces at least seven
discrete TTL devices.
o Full isolation of PCMCIA memory and I/O cards is supported to
allow safe insertion and removal of cards, both "hot" and "cold."
o PCMCIA buffer modes are completely PCMCIA 2.0-compatible.
o For single PCMCIA card support, Mode 1 buffers 20 address lines
and 5 control lines. Because of the quiet bus design of PC/CHIPm
the upper address lines can be connected directly to the PCMCIA
card slot in a single card system for full 64MB support.
o For dual PCMCIA card support, Modes 2 and 3 together buffer all
necessary address and control lines for independent 64MB support
of each card.
o Between PCMCIA cycles, the F87000 sets PCMCIA buses and control
lines to a low-power state to consume only a fraction of the power
used in a standard TTL buffer design.
o Multi-function mode (Mode 4) provides keyboard scanning, a
parallel interface, and IDE interface, a configuration latch, and
a 1.8MHz UART clock generation circuit.
o Keyboard scan interface in the multi-function mode requires only a
single external resister pack and provides an interrupt to the
system on key depression. The interface can be used instead as
general-purpose 16-bit output and 8-bit input ports.
o Parallel interface in the multi-functional mode allows high-speed,
PS/2-compatible bidirectional communication with other systems.
o Configuration latch can be used to control seven external devices
plus the UART clock divider. An additional decode line accommo-
dates an external latch for eight more device control lines.
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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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