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**82C206   Integrated Peripheral Controller                        c86
***Info:
The 82C206 Integrated Peripheral  Controller incorporates two 8237 DMA
controllers.   two  8259   Interrupt  controllers.   one  8254  Timer/
Counter.   one MC146818  Real Time  Clock, 74LS612  memory  mapper. in
addition to  several other  TTL/SSI interface logic  chips to  offer a
single  chip  integration  of  all  the peripherals  attached  to  the
peripheral  bus (X-Bus) in  the IBM  PC AT  While offering  a complete
compatibility to the IBM PC  AT architecture. the chip offers enhanced
features and  improved speed performance. These  include an additional
64 bytes of user RAM for  the Real Time Clock, and drastically reduced
recovery  specifications for the  8237, 8259  and 8254.  Variable wait
state option is  provided for the DMA cycles.  Programmable delays are
provided for the CPU access to the internal registers of the chip. The
chip also provides an option to select 8 or 4 MHz system clock.

The 82C206 along with the  (CS8220 PC AT Compatible CHIPSet provides a
highly  integrated high performance  solution for  a PC  AT compatible
implementation.

The  82C206  is  implemented  usmg  advanced CMOS  technology  and  is
packaged in an 84-pin PLCC.


***Versions:...
***Features:...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93
***Info:...
***Versions:...
***Features:
o   Fully static design substantially reduces power consumption when 
    compared to discrete TTL designs, allowing direct battery drive.
o   3.3V or 5V operation provides flexibility for system design and 
    allows dynamic 3.3/5V switching of system voltage to further 
    reduce power consumption.
o   Each F8700 device can be strapped to configure one of three 
    buffer modes or a multi-function mode, reducing parts inventory 
    requirements.
o   High integration means each F8700 mode replaces at least seven 
    discrete TTL devices.
o   Full isolation of PCMCIA memory and I/O cards is supported to 
    allow safe insertion and removal of cards, both "hot" and "cold."
o   PCMCIA buffer modes are completely PCMCIA 2.0-compatible.
o   For single PCMCIA card support, Mode 1 buffers 20 address lines 
    and 5 control lines.  Because of the quiet bus design of PC/CHIPm 
    the upper address lines can be connected directly to the PCMCIA 
    card slot in a single card system for full 64MB support.
o   For dual PCMCIA card support, Modes 2 and 3 together buffer all 
    necessary address and control lines for independent 64MB support 
    of each card.
o   Between PCMCIA cycles, the F87000 sets PCMCIA buses and control 
    lines to a low-power state to consume only a fraction of the power 
    used in a standard TTL buffer design.
o   Multi-function mode (Mode 4) provides keyboard scanning, a 
    parallel interface, and IDE interface, a configuration latch, and 
    a 1.8MHz UART clock generation circuit.
o   Keyboard scan interface in the multi-function mode requires only a 
    single external resister pack and provides an interrupt to the 
    system on key depression. The interface can be used instead as 
    general-purpose 16-bit output and 8-bit input ports.
o   Parallel interface in the multi-functional mode allows high-speed,
    PS/2-compatible bidirectional communication with other systems.
o   Configuration latch can be used to control seven external devices 
    plus the UART clock divider. An additional decode line accommo-
    dates an external latch for eight more device control lines.

**Other:...
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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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