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**F8680/A  PC/CHIP Single-Chip PC                                  c93
***Notes:...
***Info:...
***Configurations:...
***Features
o   3.3V/5V operation, fully static design, and intelligent sleep mode 
    reduce power consumption approximately 60 percent and allow direct
    battery drive.
o   PC-compatible design supports PC software and 8-bit ISA cards.
o   SuperState R mode provides a separate operating environment and 
    enables complete I/O and interrupt monitoring without BIOS 
    modification.
o   Virtual I/O feature allows device emulation as well as I/O 
    monitoring and control.
o   Virtual Interrupts feature allows interrupts to be monitored and/
    or redirected before any operating system, application program, 
    or TSR sees them.
o   26-bit address bus enables 64MB memory map and allows direct 
    support of PCMCIA  memory card.
o   Four-stage pipeline and 14MHz operation give performance 
    comparable to a 286 or 386SX system.
o   Flexible memory management supports PCMCIA cards and up to three 
    banks of PSRAM, SRAM, and/or DRAM.
o   Bank switching and high memory access overcome the 1MB addressing 
    limitation of the 8086 processor, and enable PCMCIA and EMS 
    support.
o   Single CGA controller manages a CRT or LCD panel display and 
    requires only a single 32Kx8 SRAM to minimize power consumption 
    and board space.
o   Visual Map gray scaling provides excellent visual contrast on any 
    LCD panel.
o   16C450-compatible UART supports COM1 or COM2 or can be disabled.
o   Over 100 configuration registers allow flexibility, control, and 
    differentiation in system design.

F8680A adds:

o   Full PCMCIA 2.0 memory and I/O card support ensure compatibility 
    with current and future expansions.

**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93
***Info:
The F87000  Multi-Mode Peripheral  Chip is a  companion to  the F8680A
PC/CHIP single-chip PC. By strapping  pins to select the desired mode,
the F87000 device becomes one of four integrated peripheral chips that
extend the functionality of PC/CHIP.

Chips and Technologies, Inc. has designed the F87000 chip specifically
for use  with the F8680A  microchip to accommodate  portable computing
devices   and  embedded   control   applications  where   integration,
conservation of board space, and power consumption are critical.

In  PCMCIA  card  implementations,  card buffering  and  isolation  is
recommended for  design robustness,  especially in rugged  use enviro-
nments.  The buffering ensures that  the PCMCIA card receives a strong
clean  signal, while the  isolation provides  both the  protection for
"hot card insertion" and is hardwired for turning off power to a card.
Hardware isolation,  supported with Power  Management SuperState code,
minimizes the system’s power  consumption.  PCMCIA card slots that are
not properly buffered and isolated run  a high risk of a system crash/
failure if the cards are inserted/removed while the slot is powered.

The PC/CHIP F87000 is designed to be used in four modes. 
o    Mode 1 ---- Single PCMCIA card buffering support provides:
     • 20-bit address buffer.
     • 16-bit bidirectional data buffer.
     • Buffering for five control signals.
o    Modes 2 and 3 ---- Dual PCMCIA card buffering support provides:
     • Individual address buffering (64MB each).
     • Individual data bus buffering.
     • Two OR gates.
o    Mode 4 ---- Multifunctional mode provides:
     • Keyboard circuitry interfacing to a 16 x 8 keyboard matrix.
     • Clock divider conversion of 14.31818MHz to 1.8432MHz output 
       (divide by 7.77).
     • Parallel printer port.
     • IDE interface.
     • 7-bit configuration ports plus external select for port 
       expansion.

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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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