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**82C711   Universal Peripheral Controller II                  c:Jan91
***Info:...
***Versions:...
***Features:
o   For MOTHERBOARD Applications with configuration via software
o   Low Power CMOS, 100 pin PQFP Package
o   On Chip Power Management Features, Controllable Through Hardware 
    and/or Software
o   100% IBM PC-XT/AT Compatibility.
o   24 mA IBM AT/XT Bus Interface Buffers
o   Schmitt Trigger Input on Reset Pin and FDC interface inputs
o   Two 16450 Compatible UARTs
o   1 IBM PC-XT/AT Compatible Enhanced (Bi-Directional) Parallel Port 
o   24 mA Parallel Port Output Drivers
o   IDE Interface (For Embeded AT & XT Hard drives)
o   Single 24 MHz Crystal/Oscillator for UART and Floppy Disk 
    Controller
o   Fully uPD72065B and IBM-BIOS Compatible Floppy Disk Controller
    - Licensed NEC design
    - 48 mA floppy drive interface buffers
    - Data rate and drive control registers
    - Two pin programmable precompensation modes
    - Supports two floppy drives directly and up to four with an 
      external decoder
    - DMA enable logic
o   On-Chip Precision Analog Data Separator
    - +/-380ns at 500K bps
    - +/-740ns at 250K bps
    - Automatically selects one of three filters
    - Supports 250 Kb/s, 300 Kb/s, 500 Kb/s & 1 Mb/s data rates 
o   Member of ELEATsx CHIPSet

**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91
***Info:
The 82C835 interfaces directly with the 386sx and has been designed to
work  closely with  the 82C836  single chip  AT (SCAT-sx).  The 82C835
contains  a 386sx  cache  controller incorporating  the cache  control
logic and  tag RAM.  Also included are  several programmable registers
provided for configuration options. The ability to configure the cache
organization (Two-Way Set-Associative or Direct Mapped) and size (16KB
or 32KB) allows a flexible selection of external data SRAM.

In addition to the cache  controller, the 82C835 integrates the AT I/O
channel  command and  address  buffers and  the corresponding  control
logic. Many existing 80386sx system implementations require the use of
external buffers,  latches, and transceivers to drive  and receive the
commands and addresses.  These systems also require external SSI logic
to control the operation of these buffers. Systems will typically save
six  to seven  external TTL  buffers and  five to  six SSI  gates when
implementing the channel interface with the 82C835. By integrating the
channel  drivers and  logic, the  82C835 reduces  the system  size and
complexity.

***Versions:...
***Features:...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
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*Contaq  . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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