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**82C711 Universal Peripheral Controller II c:Jan91
***Info:
The 82C711/712 Universal Peripheral Controller II (UPC II) are single
chip controllers offering a complete I/O solution for the PC-XT &
PC-AT environments. The 82C711 and 82C712 chips are nearly
operationally and pin identical.
The 82C711 supports the MOTHERBOARD application. It provides one
enhanced parallel port (printer/bi-directional), two 16450 UARTs, one
IDE XT/AT hard disk interface and floppy disk controller. The
configuration is software controllable which can be integrated into
system BIOS. Power management is done through the PWRGD pin. When the
chip is powered down (PWRGD inactive), the current drawn is less that
250 micro amp. All inputs are disabled and all outputs are
inactive. The contents of all the registers are preserved, as long as
the power supply to the 82C711 is maintained.
The 82C712 supports the ADAPTER applications. It provides one printer
port, two 16450 UARTs, IDE AT hard disk interface, floppy disk
controller, and one game port chip select.
The 82C711/712 feature 24 mA drives for the output buffers, including
the host data bus and parallel port data bus. The floppy output
drivers are capable of sinking 48mA. The host interface is PC
compatible and can be connected directly to the bus (DO-D7, A0-A9,
IOR, IOW, AEN, IRQ3, IRQ4, FINTR, PINTR, and RESET).
***Versions:...
***Features:...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91
***Info:
The 82C835 interfaces directly with the 386sx and has been designed to
work closely with the 82C836 single chip AT (SCAT-sx). The 82C835
contains a 386sx cache controller incorporating the cache control
logic and tag RAM. Also included are several programmable registers
provided for configuration options. The ability to configure the cache
organization (Two-Way Set-Associative or Direct Mapped) and size (16KB
or 32KB) allows a flexible selection of external data SRAM.
In addition to the cache controller, the 82C835 integrates the AT I/O
channel command and address buffers and the corresponding control
logic. Many existing 80386sx system implementations require the use of
external buffers, latches, and transceivers to drive and receive the
commands and addresses. These systems also require external SSI logic
to control the operation of these buffers. Systems will typically save
six to seven external TTL buffers and five to six SSI gates when
implementing the channel interface with the 82C835. By integrating the
channel drivers and logic, the 82C835 reduces the system size and
complexity.
***Versions:...
***Features:...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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