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**CS8238   CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226)   c:Aug89
***Info:...
***Configurations:...
***Features:
o   100% functionally compatible to IBM PS/2 Models 70/80 
o   Supports 16,20, and 25 MHz compatible PS/2 Models 70/80 
o   High performance Matched Memory Interface for Micro Channel 
    Memory Adapters at 16, 20 and 25 MHz 
o   Advanced Page Interleaved Memory Controller with integrated Bad 
    Block Remapping Capability 
o   Near zero wait states (average 0.5 - 0.7 wait states) 

Memory on Local Data Bus 
120 ns DRAMs at 16 MHz 
100 ns DRAMs at 20 MHz 
80  ns DRAMs at 25 MHz 

o   Integrated Lotus-Intel-Microsoft Memory Specification (LIM EMS 
    3.2) 
    Memory Controller with 4 register sets, expandable to full LIM 
    EMS 4.0 specification with 8 register sets of 64 mapping 
    registers using the 82C631 EMS mapper chip. 
o   Supports IBM Matched Memory Cycle and CHIPS Fast Micro Channel 
    Matched Memory Cycle. 
o   High performance, Fast VGA interface to the 82C451 and 82C452 
    VGA controllers. 
o   Asynchronous CPU and DMA state machines. 
o   PS/2 Model 70/80 compatible Address Recovery logic. 
o   Low power, high speed CMOS technology. 

**CS82310  PEAK/DM 386 AT           (82C351/82C355/82C356)         c91...
**CS8281   NEATsx (386SX)           (82C811/812/215/206)       c:Dec89...
**CS8283   LeAPset-sx               (82C841/82C242/82C636)     c:Mar90...
**CS8285   PEAKsx                   (82C836/82C835)                c91...
**CS8288   CHIPSlite-sx             (82C836/82C641/82C835)          c?...
**CS4000   WinCHIPS                 (64200/84021/84025)            c92...
**CS4021   ISA/486                  (84021/84025)                  c92...
**CS4031   CHIPSet                  (84031/84035)              5/10/93...
**CS4041/5 CHIPSet                  (84041/84045)              2/10/95...
**CB8291   ELEAT                    [no datasheet]                 c90...
**CB8295   ELEATsx                  [no datasheet]                 c90...
**82C100   IBM PS/2 Model 30/Super XT                                ?...
**82C110   IBM PS/2 Model 30/Super XT                                ?...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91
***Info:
The 82C835 interfaces directly with the 386sx and has been designed to
work  closely with  the 82C836  single chip  AT (SCAT-sx).  The 82C835
contains  a 386sx  cache  controller incorporating  the cache  control
logic and  tag RAM.  Also included are  several programmable registers
provided for configuration options. The ability to configure the cache
organization (Two-Way Set-Associative or Direct Mapped) and size (16KB
or 32KB) allows a flexible selection of external data SRAM.

In addition to the cache  controller, the 82C835 integrates the AT I/O
channel  command and  address  buffers and  the corresponding  control
logic. Many existing 80386sx system implementations require the use of
external buffers,  latches, and transceivers to drive  and receive the
commands and addresses.  These systems also require external SSI logic
to control the operation of these buffers. Systems will typically save
six  to seven  external TTL  buffers and  five to  six SSI  gates when
implementing the channel interface with the 82C835. By integrating the
channel  drivers and  logic, the  82C835 reduces  the system  size and
complexity.

***Versions:...
***Features:...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
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*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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