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**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?
***Info:...
***Configurations:
M1541/M1542 System Controller
M1533/M1543 PCI-to-ISA Bus Bridge

M1541 + M1533
M1541 + M1543
M1542 + M1533
M1542 + M1543

See the M1531 section for details on the M1533.

The datasheet  is very confusing  as it does  not state how  the terms
M1531, M1532, Aladdin V and Aladdin V+ relate to each other. According
to:
http://pclinks.xtreemhost.com/chipsets_pentium.htm

The Aladdin V and Aladdin V+ names are both associated with the M1541.
The M1541 has 5 revisions, A  thru E.  The M1542 part number is assoc-
iated with revision  F onwards. The main difference  with the M1542 is
that it now can cache 512MB  of RAM, instead of only 128MB.  The diff-
erence between the Aladdin V and  Aladdin V+ is that the V+ officially
supports a 100 MHz bus, the V only 83.3 MHz.

However, none of this information can be derived from the datasheets
used to write the info and features section. 

***Features:...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91
***Info:
The 82C835 interfaces directly with the 386sx and has been designed to
work  closely with  the 82C836  single chip  AT (SCAT-sx).  The 82C835
contains  a 386sx  cache  controller incorporating  the cache  control
logic and  tag RAM.  Also included are  several programmable registers
provided for configuration options. The ability to configure the cache
organization (Two-Way Set-Associative or Direct Mapped) and size (16KB
or 32KB) allows a flexible selection of external data SRAM.

In addition to the cache  controller, the 82C835 integrates the AT I/O
channel  command and  address  buffers and  the corresponding  control
logic. Many existing 80386sx system implementations require the use of
external buffers,  latches, and transceivers to drive  and receive the
commands and addresses.  These systems also require external SSI logic
to control the operation of these buffers. Systems will typically save
six  to seven  external TTL  buffers and  five to  six SSI  gates when
implementing the channel interface with the 82C835. By integrating the
channel  drivers and  logic, the  82C835 reduces  the system  size and
complexity.

***Versions:...
***Features:...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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