[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90
***Info:...
***Configurations:...
***Features:
o 100% IBM PC AT Cache based 386/AT Compatible CHIPSet
o Supports 16, 20, 25 and 33 MHz 80386DX based Systems
o Independent clock to support correct AT bus timing
o Flexible architecture allows usage in any iAPX 386 design
o A complete 386/AT Cache based PC AT now requires only 19 IC's
plus memory
o Integrates Cache Directory and CPU/Cache/DRAM Controller on a
single chip to provide PEAK integration and PEAK performance.
o Integrated CPU/Cache/DRAM Controller enhances 80386DX CPU and
memory system performance
- Averages to nearly zero wait state memory access
- Zero wait state non-pipelines read hit access
- Zero wait state non-pipelined write access
- Buffered-write through DRAM update scheme to minimize write
cycle penalty
- Cache hit rate up to 99%
o Supports 32KB, 64KB, and 128KB two-way set associative cache
organization
- 32 byte line size
- 4 byte sub-line size with associative valid bit
- Support blocks (of variable size - 4KB to 4M) of main memory
as non-cacheable
address space
- Supports caching of data and code
o Tightly coupled 80386DX interface
- Deigned to interface directly with the 80386DX
- Supports 16, 20, 25 and 33MHz operation
- Integrated support for 80387DX a Weitek 3167 coprocessor
o Flexible memory architecture to support:
- Memory configurations up to 128 MB
- Programmable DRAM wait states
- 256K, 1MB, and 4MB DRAMs in configurations of up to 4 blocks
and 8 banks
- Staggered RAS during refresh
- Hidden refresh and burst refresh
- 256K/512K/1M PROMs
o Supports shadowing of BIOS EPROMs
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93
***Info:
The CHIPS 82C735 enhanced I/O peripheral controller is a single-chip
solution offering complete I/O capabilities for PC/AT and PC/XT
motherboard applications. The controller is configured via
software. The 82C735 features a floppy disk controller, a digital data
separator, two 16550 compatible UARTs, an enhanced bidirectional
parallel port interface called Printgine, IDE interface control logic,
and a game port chip select. For more information about these
systems, see the Functional Description [see datasheet].
4MB FLOPPY DISK CONTROLLER
The floppy disk controller is software compatible with 765B and 82077
controller functions. It provides a 4MB perpendicular recording format
as well as the standard floppy drive format for 5.25-inch and 3.5-inch
media. The controller supports two drives directly and up to four
drives with an external decoder.
DIGITAL DATA SEPARATOR
The digital data separator is capable of data transfer rates up to
1MB/sec and requires no external components.
NS16550 UARTS AND IDE
The two licensed NS16550 UARTs are improved versions of the NS16450
UARTs. They are provided with individual 16-byte FIFOs to relieve the
CPU of excessive software overhead and are still capable of running
existing 16450 software.
The IDE control logic provides a complete IDE interface for embedded
hard disk drives.
MOUSE PORT LOGIC
The 82C735 controller features optional PS/2 style mouse port logic
with BIOS and driver support. Only one of the UARTs can be used when
the mouse is operational.
PRINTGINE PARALLEL PORT INTERFACE
The parallel port interface, Printgine, is a multiprotocol interface
capable of supporting both unidirectional and bidirectional transfer
modes. It is fully compatible with ISA and PS/2 in the standard modes,
and also supports Microsoft ECP, EPP, and fast Centronics in the
enhanced modes. The output on the control pins switch to become
bidirectional TTL drivers in the fast modes. This makes the port run
faster than is possible with the open-drain drivers provided for the
standard modes.
Printgine provides an economical mechanism for significantly improving
the throughput of an improved parallel port that is upward compatible
with the existing parallel port. The interface can operate in five
different modes: standard (ISA-style unidirectional), bi-di
(PS/2-style bidirectional), Microsoft ECP, EPP, and fast
Centronics. The standard and bi-di modes are compatible with existing
parallel port protocols.
The ECP, EPP, and fast Centronics protocols are enhanced bidirectional
modes that achieve dramatic improvement by implementing the protocols
in hardware. The fast Centronics mode is capable of a data transfer
rate of 200KB/sec, while the ECP and EPP modes are capable of data
transfer rates of 2MB/sec, compared to 15KB/sec in the standard mode.
POWER MANAGEMENT
The 82C735 is provided with several power management features that are
controllable through hardware or software. In hardware, the device
can be completely powered down through a powerdown pin. In this mode,
all inputs are disabled, all outputs are inactive, and the contents of
all registers are preserved (as long as the power supply is
maintained). In software, the device allows each port to be powered
down independently.
***Versions:...
***Features:...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved