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**M1217/M1209    386SX/SLC Single Chip (40MHz)    [no datasheet]   c91
***Notes:...
**M1219          386DX/486 ISA Cache? Single Chip [no datasheet]     ?
**M1419          386DX/486 ISA Cache  Single Chip [no datasheet]   c91
**Ml429/31/35    486 VLB/PCI/ISA      [no datasheet, some info] cOct93...
**M1439/31/45    486 VLB/PCI/ISA      [no datasheet, some info] <May95...
**M1489/87       FinALi-486 PCI Chipset                         <Feb95...
**M????          Genie, Quad Pentium  [no datasheet, some info]    c95...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93
***Info:...
***Versions:...
***Features:
Floppy Disk Controller
o   Single-chip floppy solution
o   Software compatible with NEC 765B and Intel 82077
o   Perpendicular recording support
o   48mA disk drivers and Schmitt-trigger inputs
o   Direct support for two drives, and up to four drives with external 
    decoder
o   Enhanced digital data separator
o   No external filter components required
o   Support for 250KB/s, 300KB/s, 500KB/s and 1MB/sec data rates
o   Primary and secondary floppy address port selects

Serial Ports
o   Two NS16550 compatible UARTs
o   16-byte FIFO
o   Modem control circuitry
o   Optional PS/2 type mouse port logic operated under BIOS and 
    software driver control

IDE Interface
o   Provides a complete IDE interface for embedded hard disk drives.
o   Primary and secondary IDE address port selects.

Parallel Port----Printgine
o   Multiprotocol parallel port interface, P1284-compatible 
o   Compatible with IBM PC, XT, AT, and PS/2 architectures
o   Standard and bidirectional parallel port
o   Microsoft and Hewlett-Packard Extended Capabilities Port (ECP), 
    Enhanced 
    Parallel Port (EPP), and fast Centronics protocols support
o   Transfer rates up to 2MB/sec possible with fast protocols
o   Protocols implemented in hardware to reduce software overhead
o   24mA parallel port output drivers
o   128-byte FIFO

General
o   100-percent compatible with IBM PC, XT and AT architectures
o   24mA AT/XT bus interface buffers
o   Game port and general purpose chip select logic
o   On-chip power management features, controllable through hardware 
    and/or software
o   Configuration via software
o   100-pin QFP package

**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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