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**Intro:
The information  contained within this  file should not  be considered
100%  correct.   Where  possible   information  has  been  taken  from
datasheets, however  even this info  may be incorrect.  The datasheets
state what  the chip should  do, not what  they actually do.  This is,
compounded further by different revisions of chips.

This  document will  never be  complete, and  I have  no intention  of
finding every  datasheet for  every chip  set. Some  of the  chip sets
listed are  from later systems  in the PIII/P4/Athlon era.   There are
many websites  with information on  these chip sets and  these entries
will likely not be expanded upon.  The focus of this document is early
PC/XT to  Pentium chip sets.  There are  few sites that  clearly illu-
strate this information, and how they relate to each other.

I  aim  to  prioritize   cataloging  significant,  rare  or  otherwise
interesting chip sets.

BTW the reason I wrote all of this down, is so that I could FORGET it.
Basically I needed to free  up some RAM.  I've  a head full  of arcane
snippets of  information on this subject.   I don't want to  end up  a
crazy old man  ranting random disjointed information  ("The C&T CS8220
came before the CS8221 you KNOW!") to disinterested passersby,  unable
to see how senile I've become. A side benefit, this might be useful to
someone else:-)

**Quote style:...
**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:
date source: TimelineDateSort7_05.pdf.

Also states:  82395SX (8-kilobyte);  82396SX (16-Kbyte);  Extension of
386(TM) Smart cache architecture with two new versions of cache memory
controllers.  Designed for  20-megahertz  Intel386 SX  microprocessor-
based systems

Could not find datasheet, see 82396SX, YMMV.

**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

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