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**82C110   IBM PS/2 Model 30/Super XT                                ?
***Notes:...
***Info:
The 82C110 is a single chip implementation of most of the system logic
necessary to implement a super XT compatible system with PS/2 Model 30
functionality using either an  8086 or 8088 microprocessor. The 82C110
can  be used  with either  8  or 16-bit  microprocessors.  The  82C110
includes features  which will enable  the PC manufacturer to  design a
super PS/2 Model 30/XT  compatible system with the highest performance
at  10  MHz  zero  wait   state  system  with  an  8086,  the  highest
functionality  with  dual  clock  and  2.5 MB  DRAM  {with  integrated
Extended Memory  System control  logic}, the highest  integration with
the lowest component count SMT design.

The 82C110 can be combined with-CHIPs’ 82C601 Multifunction Controller
and 82C451 VGA Graphics Controller to provide a high performance, high
integration PS/2 Model 30 type system.

The 82C110 supports most of the peripheral functions on the PS/2 Model
30 planar board; 8284 compatible  clock generator with the option of 2
independent  oscillators, 8288 compatible  bus controller,  8237 comp-
atible  DMA  controller, 8259  compatible  interrupt controller,  8254
compatible  timer/counter,  8255 compatible  peripheral  I/O port.  XT
Keyboard interface, Parity Generation and Checking for DRAM memory and
memory controller for DRAM memory sub-system.

The  82C110 enables  the  user to  add  PS/2 Model  30 superset  func-
tionality on the planar board: dual clock, with synchronized switching
between  the two,  clocks.  built-in  Lotus-Intel-Microsoft  (LIM) EMS
support for up to 2.5 Megabytes of DRAM.

The  82C110 supports a  very flexible  memory architecture.   The DRAM
controller  supports 64K,  256K  and  1M DRAMs.   These  DRAMs gen  be
organized in  four banks of up  to a maximum  of 2.5 MB on  the planar
board. The  2.5 MB memory can  be implemented with  2 banks of 7M  X 1
DRAMs, partitioned locally as 540KB of real memory and 1,875 MB of EMS
memory. The 82C110 is packaged in a 100-pin plastic flatpack.

***Configurations:...
***Features:...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93
***Info:
The CHIPS  82C721 enhanced I/O peripheral controller  is a single-chip
solution  offering  complete  I/O  capabilities for  PC/AT  and  PC/XT
environments.  The  82C721   supports  motherboard  applications  with
configuration via software.

The  82C721  features  a   floppy  disk  controller,  a  digital  data
separator, two 16450 compatible UARTs, a bi-directional parallel port,
an IDE interface control logic and a game port chip select.

The floppy  disk controller is software compatible  with NEC uPD72065B
floppy  disk controller.  The  controller supports  up to  four drives
directly. The digital data separator is capable of data transfer rates
up to 500kb/sec and requires no external components.

The 82C721 has two UARTs  which are compatible with NS16450 UARTs. The
IDE control logic provides a  complete IDE interface for embedded hard
disk  drives.  The  bidirectional  parallel  port  maintains  complete
compatibility with ISA and PS/2  parallel ports.  It can be configured
for either output mode or for bidirectional mode.

The  configuration   RAM  and  circuitry   support  programmable  base
addresses for  all the registers. Selection of  sources of interrupts,
enabling and configuring of on-chip  subsystems and the control of the
configuration  process itself  are also  handled by  this RAM  and its
associated circuitry.  The game port chip select provides a predefined
I/O address decode for games and joy stick applications.

The 82C721,  designed for  motherboard applications, is  provided with
several  power  management features,  which  are controllable  through
hardware  or  software. In  hardware,  the  device  can be  completely
powered down through  a power-down pin.  In this  mode, all inputs are
disabled, all outputs are inactive,  and the contents of all registers
are  preserved  (as long  as  the  power  supply is  maintained).   In
software,   the  device   allows  each   port  to   be   powered  down
independently.

The  82C721 features 24mA  drivers for  output buffers,  including the
host  data bus  and  the parallel  port  data bus.  The floppy  output
drivers  are  capable  of  sinking  48mA. The  host  interface  is  PC
compatible and can be connected directly to the ISA bus.

***Versions:...
***Features:...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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