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**82C100 IBM PS/2 Model 30/Super XT ?
***Info:
The 82C100 is a single chip implementation of most of the system logic
necessary to implement a super XT compatible system with PS/2 Model 30
functionality using either an 8086 or 8088 microprocessor. The 82C100
can be used with either 8 or 16-bit microprocessors. The 82C100
includes features which will enable the PC manufacturer to design a
super PS/2 Model 30/XT compatible system with the highest performance
at 10 MHz zero wait state system with an 8086, the highest
functionality With dual clock and 2.5 MB DRAM (with integrated
Extended Memory System control logic), the lowest power implementation
by utilizing the on-chip power management features and the highest
inte- gration with the lowest component count SMT design.
The 82C100 can be combined with CHIPs‘ 820601 Multifunction Controller
and 82C451 VGA Graphics Controller to provide a high performance, high
integration PS/2 Model 30 type system.
The 82C100 supports most of the peripheral functions on the P8/2 Model
30 planar board: 8284 compatible clock generator with the option of 2
independent oscillators. 8288 compatible bus controller, 8237 comp-
atible DMA controller, 8259 compatible interrupt controller, 8254
compatible timer/counter, 8255 compatible peripheral I/O port, XT Key-
board interface, Parity Generation and Checking for DRAM memory and
memory controller for DRAM and SRAM memory sub-systems.
The 82C100 enables the user to add P8/2 Model 30 superset
functionality on the planar board: dual clock with synchronized
switching between the two clocks, built-in Lotus-Intel-Microsoft (LIM)
EMS support for up to 2.5 Megabytes of DRAM and power management
features for SLEEP mode as well as SUSPEND/RESUME Operations. The
SLEEP and SUSPEND/RESUME features help in preserving the battery life
in laptop portable applications.
The 82C100 Supports a very flexible memory architecture. For systems
with DRAMs, the DRAM controller supports 64K, 256K and 1M DRAMs. These
DRAMs can be organized in four banks of up to a maximum of 2.5 MB on
the planar board. The 2.5 MB memory can be implemented with 2 banks
of 1M x 1 DRAMs, partitioned locally as 640KB of real memory and
1.875MB of EMS memory, For systems which require low operating power
and minimum standby power dissipation, the chips provide the decode
logic which in conjunction with external decoders allows selection of
up to 640KB of static RAM. This option is useful in laptop portable
applications.
The 82C100 is packaged in a 100-pin plastic flatpack.
***Configurations:...
***Features:...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91
***Info:
The 82C711/712 Universal Peripheral Controller II (UPC II) are single
chip controllers offering a complete I/O solution for the PC-XT &
PC-AT environments. The 82C711 and 82C712 chips are nearly
operationally and pin identical.
The 82C711 supports the MOTHERBOARD application. It provides one
enhanced parallel port (printer/bi-directional), two 16450 UARTs, one
IDE XT/AT hard disk interface and floppy disk controller. The
configuration is software controllable which can be integrated into
system BIOS. Power management is done through the PWRGD pin. When the
chip is powered down (PWRGD inactive), the current drawn is less that
250 micro amp. All inputs are disabled and all outputs are
inactive. The contents of all the registers are preserved, as long as
the power supply to the 82C711 is maintained.
The 82C712 supports the ADAPTER applications. It provides one printer
port, two 16450 UARTs, IDE AT hard disk interface, floppy disk
controller, and one game port chip select.
The 82C711/712 feature 24 mA drives for the output buffers, including
the host data bus and parallel port data bus. The floppy output
drivers are capable of sinking 48mA. The host interface is PC
compatible and can be connected directly to the bus (DO-D7, A0-A9,
IOR, IOW, AEN, IRQ3, IRQ4, FINTR, PINTR, and RESET).
***Versions:...
***Features:...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
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