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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C711   Universal Peripheral Controller II                  c:Jan91
***Info:
The 82C711/712 Universal Peripheral  Controller II (UPC II) are single
chip  controllers offering  a complete  I/O solution  for the  PC-XT &
PC-AT   environments.  The   82C711   and  82C712   chips  are   nearly
operationally and pin identical.

The  82C711  supports the  MOTHERBOARD  application.  It provides  one
enhanced parallel port  (printer/bi-directional), two 16450 UARTs, one
IDE  XT/AT  hard  disk  interface  and  floppy  disk  controller.  The
configuration is  software controllable which can  be integrated into
system BIOS. Power management is  done through the PWRGD pin. When the
chip is powered down (PWRGD  inactive), the current drawn is less that
250  micro  amp.   All  inputs  are  disabled  and   all  outputs  are
inactive. The contents of all  the registers are preserved, as long as
the power supply to the 82C711 is maintained.

The 82C712 supports the  ADAPTER applications. It provides one printer
port,  two  16450 UARTs,  IDE  AT  hard  disk interface,  floppy  disk
controller, and one game port chip select.

The 82C711/712 feature 24 mA  drives for the output buffers, including
the  host data  bus  and parallel  port  data bus.  The floppy  output
drivers  are  capable  of  sinking  48mA. The  host  interface  is  PC
compatible and  can be connected  directly to the bus  (DO-D7, A0-A9,
IOR, IOW, AEN, IRQ3, IRQ4, FINTR, PINTR, and RESET).

***Versions:...
***Features:...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...