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**82C100 IBM PS/2 Model 30/Super XT ?
***Info:
The 82C100 is a single chip implementation of most of the system logic
necessary to implement a super XT compatible system with PS/2 Model 30
functionality using either an 8086 or 8088 microprocessor. The 82C100
can be used with either 8 or 16-bit microprocessors. The 82C100
includes features which will enable the PC manufacturer to design a
super PS/2 Model 30/XT compatible system with the highest performance
at 10 MHz zero wait state system with an 8086, the highest
functionality With dual clock and 2.5 MB DRAM (with integrated
Extended Memory System control logic), the lowest power implementation
by utilizing the on-chip power management features and the highest
inte- gration with the lowest component count SMT design.
The 82C100 can be combined with CHIPs‘ 820601 Multifunction Controller
and 82C451 VGA Graphics Controller to provide a high performance, high
integration PS/2 Model 30 type system.
The 82C100 supports most of the peripheral functions on the P8/2 Model
30 planar board: 8284 compatible clock generator with the option of 2
independent oscillators. 8288 compatible bus controller, 8237 comp-
atible DMA controller, 8259 compatible interrupt controller, 8254
compatible timer/counter, 8255 compatible peripheral I/O port, XT Key-
board interface, Parity Generation and Checking for DRAM memory and
memory controller for DRAM and SRAM memory sub-systems.
The 82C100 enables the user to add P8/2 Model 30 superset
functionality on the planar board: dual clock with synchronized
switching between the two clocks, built-in Lotus-Intel-Microsoft (LIM)
EMS support for up to 2.5 Megabytes of DRAM and power management
features for SLEEP mode as well as SUSPEND/RESUME Operations. The
SLEEP and SUSPEND/RESUME features help in preserving the battery life
in laptop portable applications.
The 82C100 Supports a very flexible memory architecture. For systems
with DRAMs, the DRAM controller supports 64K, 256K and 1M DRAMs. These
DRAMs can be organized in four banks of up to a maximum of 2.5 MB on
the planar board. The 2.5 MB memory can be implemented with 2 banks
of 1M x 1 DRAMs, partitioned locally as 640KB of real memory and
1.875MB of EMS memory, For systems which require low operating power
and minimum standby power dissipation, the chips provide the decode
logic which in conjunction with external decoders allows selection of
up to 640KB of static RAM. This option is useful in laptop portable
applications.
The 82C100 is packaged in a 100-pin plastic flatpack.
***Configurations:...
***Features:...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90
***Notes:...
***Info:
The 82C601 single chip peripheral controllers is the second generation
of our Multifunction Controller product line.
This chip is an LSI implementation of the most commonly used
peripheral devices found in an IBM PC, XT or AT. The chip features 16
mA drivers for the output buffers, such as the host data bus and
parallel port data bus. It incorporates two 16450 compatible UARTs,
one enhanced parallel port (with bi-directional capability), and IDE
compatible hard disk interface and various chip selects (in the
MOTHERBOARD Application) or select pins and Game port decodes (in the
ADAPTER Application). Decoding logic and support for main, auxiliary
and standby power supplies and software configurable base addresses
for these devices, operational modes and interrupts are also
included. This chip supports 2 applications:
MOTHERBOARD Application where all the ports are relocatable. An
Integrated Drive electronics Interface, and various Chip Selects
(Floppy Disk, Real Time Clock and a General Purpose) have been added
for this mode. Power management aspects of the 82C601 in the
MOTHERBOARD Application include modular power down through PWRGD
pin. When the chip is powered down (i.e. when PWRGD is inactive) the
current draw should be less than 50 micro-Amps, all the inputs are
disabled, and all outputs are tri-stated. the contents of all the
registers are preserved, as long as power supply to the 82C601 is
maintained.
ADAPTER Application where the base address for the ports are
determined by the select pins (PSPz, SSPs, ASPs, and PPS); except for
game port, it is fixed @ 200H- 207H. -GAMERD and -GAMEWR outputs are
provided to minimize external gate count.
The host interface is PC compatible, i.e. DO-D7, A0-A9, -IOR, -IOW,
AEN, INTR1, INTR2, INTR3, INTR4, and RESET, and can be connected
directly to the bus. The data buffers (DO-D7, PD0-PD7, IDED7) are
capable of sinking 16 mA @ 0.5v, the parallel port control signals are
open collector with internal pull up resistors; and are capable of
sinking 16 mA @ 0.5V.
The UARTs implement fully functional serial links. Programmable
character length, parity generation and detection, stop-bit generation
and baud rate generation are provided. Double buffering is used so
that precise synchronization is unnecessary. Status information is
accessible to the CPU by reading internal registers. MODEM control
lines are provided, as are internal diagnostic functionality and
interrupt prioritization. Support for an auxiliary power system (such
as that derived from a telephone line or RS232 link) permits an 82C601
in a battery-powered device to consume no battery power until an
incoming character is detected.
The parallel port can be configured for output only (printer
application) or input and output (bi-direction}.
The configuration RAM and circuitry support programmable base
addresses for all registers internal to the chip. This permits
creation of a menu-driven program for system configuration. Selection
of sources for interrupts; enabling and configuring of on-chip
subsystems (UARTS. parallel port. etc.) and control of the
configuration process itself are also handled with this RAM and its
associated circuitry. The remainder of this data sheet will consider
each of the aforesaid subsystems individually. Sections containing
more general design data for the chip as a whole are at the end along
with electrical and physical characteristics.
***Versions:...
***Features:...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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