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**Spelling errors/mistyped words
Yes, I  know there are  spelling errors,  and things are  mistyped. It
seems no matter  how hard I try  my fingers hit 't'  twice when typing
'compatible' rendering it 'compattible' numerous, (thousands actually)
times.  I  don't have the  time or the will  to check the  spelling of
everything. Basic spell checking has been peformed. Please let me know
if  there is  anything that  would lead  to incorrect  information, or
something  is so  mangled  that  it needs  revising.  But  if you  can
basically  understand  what was  intended,  just  cope with  it.  Just
cope:-)

BTW, "110" port is  an "I/O" port that has been OCRed  badly, as is an
"1/0" port.

**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91
***Info:...
***Versions:...
***Features:
o   Cost effective Windows Accelerator
o   Interfaces directly with X86 SX/DX/DX2 Systems
o   Interfaces directly with ISA486 CHIPSet
o   High performance achieved via direct access frame buffer Memory 
    Bus Architecture
o   Direct linear mapping of entire video memory anywhere in system 
    memory space
o   Flexible video memory configurations:  8, 16, or 32-bit wide 
    VRAM (256KB–2MB)
o   Supports the following display modes with 1MB of VRAM:
    • 8bpp up to 1024x768 (interlaced or non-I/L)
    • 16bpp up to 800x600 (with Sierra RAMDAC)
    • 24bpp up to 640x480 (with Bt484 or equiv)
o   Supports higher resolution display modes with 2MB VRAM:
    • 8bpp up to 1280x1024 (non-interlaced)
    • 16bpp up to 1024x768 (interlaced or non-I/L)
    • 24bpp up to 800x600 (non-interlaced)
o   Highly integrated design (non-multiplexed system bus, direct bus 
    drive, minimum external glue logic)
o   All video shifting performed on-chip to allow use of low-cost VGA 
    RAMDACs (allows video rates to 80 MHz)
o   Compatible with high-resolution color palette RAMDACs such as the 
    Bt484 and TI 34075 having separate 8-bit and 32-bit parallel 
    inputs for direct connection to VRAM serial data (allows video 
    rates to 135 MHz)
o   Full VGA compatibility
o   Interfaces directly with the 82C481 True-Color Graphics 
    Accelerator
o   Direct interface to 82C404 programmable clock 
o   In-Circuit Testability Features
o   Small low-cost package:  EIAJ-standard 160-pin plastic flat pack
o   Chip pinouts optimized for PCB layo


**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...