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**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?
***Info:...
***Configurations:...
***Features:...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**F8680/A  PC/CHIP Single-Chip PC                                  c93
***Notes:...
***Info:...
***Configurations:...
***Features
o   3.3V/5V operation, fully static design, and intelligent sleep mode 
    reduce power consumption approximately 60 percent and allow direct
    battery drive.
o   PC-compatible design supports PC software and 8-bit ISA cards.
o   SuperState R mode provides a separate operating environment and 
    enables complete I/O and interrupt monitoring without BIOS 
    modification.
o   Virtual I/O feature allows device emulation as well as I/O 
    monitoring and control.
o   Virtual Interrupts feature allows interrupts to be monitored and/
    or redirected before any operating system, application program, 
    or TSR sees them.
o   26-bit address bus enables 64MB memory map and allows direct 
    support of PCMCIA  memory card.
o   Four-stage pipeline and 14MHz operation give performance 
    comparable to a 286 or 386SX system.
o   Flexible memory management supports PCMCIA cards and up to three 
    banks of PSRAM, SRAM, and/or DRAM.
o   Bank switching and high memory access overcome the 1MB addressing 
    limitation of the 8086 processor, and enable PCMCIA and EMS 
    support.
o   Single CGA controller manages a CRT or LCD panel display and 
    requires only a single 32Kx8 SRAM to minimize power consumption 
    and board space.
o   Visual Map gray scaling provides excellent visual contrast on any 
    LCD panel.
o   16C450-compatible UART supports COM1 or COM2 or can be disabled.
o   Over 100 configuration registers allow flexibility, control, and 
    differentiation in system design.

F8680A adds:

o   Full PCMCIA 2.0 memory and I/O card support ensure compatibility 
    with current and future expansions.

**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
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*General Sources:...