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**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89
***Info:
The CS8281 NEATsx CHlPSet, which is composed of four VLSI devices, is
a high-performance, 100%-compatible enhanced implementation of the
control logic used in the IBM PC AT. The flexible architecture of the
NEATsx CHIPSet allows it to be used as the basis for any
386sx-compatible system.
The CS8281 NEATsx CHIPSet provides a complete 386sx PC/AT compatible
system, requiring only 24 logic components plus memory devices.
The CS8281 NEATsx CHIPSet consists of the 82C811 CPU/bus controller,
the 82C812 page/interleave and EMS memory controller, the 82C215
data/address buffer, and the 82C206 integrated peripherals controller
(IPC).
The NEATsx CHIPSet supports a local CPU bus, a 16-bit system memory
bus, and the AT buses as shown in the NEATsx system block diagram [see
datasheet]. The 82C811 provides synchronization and control signals
for all buses. The 82C811 also provides an independent AT bus clock
and allows for dynamic selection between the processor clock and a
user~selectable AT bus clock. Because command delays and wait states
are configured by software, peripheral boards are provided with
maximum flexibility.
The 82C812 page/interleave and EMS memory controller provides an
interleaved memory subsystem design with page mode operation. It sup-
ports up to 8MB of DRAM with combinations of 256Kb and 1Mb DRAMs. The
processor can operate at 16 MHz with 0.7 wait state memory accesses,
using 100 nsec DRAMs. This is possible through a page interleaved
memory scheme. A RAM shadowing feature allows faster execution of
EPROM stored BIOS code by downloading and executing code from RAM. in
a DOS environment memory above 1MB can be used as EMS memory.
The 82C215 data/address buffer provides buffering and latching between
the local CPU address bus and the peripheral address bus. It also
provides buffering between the local CPU data bus and the memory data
bus. Parity bit generation and error detection logic resides in the
82C215.
The 82C206 integrated peripherals controller is an integral part of
the NEATsx CHIPSet. It is described in the 82C206 data book.
System Overview
The CS8281 NEATsx CHIPSet is designed for use in 12-16 MHz 80386 based
systems and provides complete support for the IBM PC AT bus. Four
buses are supported by the CS8281 NEATsx CHIPSet: the CPU local bus (A
and D); the system memory bus (MA and MD); the I/O channel bus (SA and
SD); and the X bus (XA and XD). The system memory bus provides an
interface between the CPU and the DRAMs and EPROMS controlled by the
82C812. The I/O channel bus refers to the bus supporting the
AT-compatible bus adapters which can be either 8- or 16-bit devices.
The X bus is the peripheral bus to which the 82C206 IPC and other
peripherals are attached in an IBM PC AT.
***Configurations:...
***Features:...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?
***Info:
The 82C100 is a single chip implementation of most of the system logic
necessary to implement a super XT compatible system with PS/2 Model 30
functionality using either an 8086 or 8088 microprocessor. The 82C100
can be used with either 8 or 16-bit microprocessors. The 82C100
includes features which will enable the PC manufacturer to design a
super PS/2 Model 30/XT compatible system with the highest performance
at 10 MHz zero wait state system with an 8086, the highest
functionality With dual clock and 2.5 MB DRAM (with integrated
Extended Memory System control logic), the lowest power implementation
by utilizing the on-chip power management features and the highest
inte- gration with the lowest component count SMT design.
The 82C100 can be combined with CHIPs‘ 820601 Multifunction Controller
and 82C451 VGA Graphics Controller to provide a high performance, high
integration PS/2 Model 30 type system.
The 82C100 supports most of the peripheral functions on the P8/2 Model
30 planar board: 8284 compatible clock generator with the option of 2
independent oscillators. 8288 compatible bus controller, 8237 comp-
atible DMA controller, 8259 compatible interrupt controller, 8254
compatible timer/counter, 8255 compatible peripheral I/O port, XT Key-
board interface, Parity Generation and Checking for DRAM memory and
memory controller for DRAM and SRAM memory sub-systems.
The 82C100 enables the user to add P8/2 Model 30 superset
functionality on the planar board: dual clock with synchronized
switching between the two clocks, built-in Lotus-Intel-Microsoft (LIM)
EMS support for up to 2.5 Megabytes of DRAM and power management
features for SLEEP mode as well as SUSPEND/RESUME Operations. The
SLEEP and SUSPEND/RESUME features help in preserving the battery life
in laptop portable applications.
The 82C100 Supports a very flexible memory architecture. For systems
with DRAMs, the DRAM controller supports 64K, 256K and 1M DRAMs. These
DRAMs can be organized in four banks of up to a maximum of 2.5 MB on
the planar board. The 2.5 MB memory can be implemented with 2 banks
of 1M x 1 DRAMs, partitioned locally as 640KB of real memory and
1.875MB of EMS memory, For systems which require low operating power
and minimum standby power dissipation, the chips provide the decode
logic which in conjunction with external decoders allows selection of
up to 640KB of static RAM. This option is useful in laptop portable
applications.
The 82C100 is packaged in a 100-pin plastic flatpack.
***Configurations:...
***Features:...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
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*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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