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**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89
***Info:
CHIPS/280 is a 7-device, enhanced CMOS implementation of most of the
system logic necessary to implement personal computers compatible to
IBM PS/2 Model 70/80. CHIPS/280 enables OEMs to offer compatible PS/2
models 70/80, that are more integrated and superior in performance
than IBM's Model 70/80.
CHIPS/280 includes the CS8238 System Logic CHIPSet, the 82C607
Multi-Function Controller with Analog Data Separator and 16550
compatible serial port, and the Enhanced Gate-Level Compatible
82C451/452 VGA chip as indicated in Figures 1a and lb [see data
sheet]. With these 7 VLSI devices, it requires only 59 additional
components plus memory to implement compatible PS/2 Models 70/80
superior to IBM's models.
CHIPS/280 is designed to maximize the performance of the 80386
microprocessor by coupling it to a high performance page/interleaved
memory sub-system. The maximum page size supported by the CHIPS/280
architecture is 16 KBytes when 1 Mbyte DRAMs are used (16 MB of
onboard Memory) and the four way interleaved mode of operation is
selected. When executing within a page, the DRAM memory sub-system can
execute at the same speed as the processor. To the 386, the mem- ory
sub-system appears as a 16 KByte direct mapped cache, using relatively
inexpensive DRAMs. When operating at 16, 20 or 25 MHZ, the average
waitstate incurred is less than 0.7. Additionally, by using Shadow RAM
techniques, the BIOS code can also be executed with near zero wait
states.
In addition to the high performance memory interface, CHIPS/280
supports a fast Matched Memory Cycle reducing the access time from 200
ns to 120 ns at 25 MHz. CHIPS proprietary Fast VGA cycle allows VGA
I/O accesses to be performed within 187.5 ns@ 16 MHz, 150 ns @ 20 MHz,
and 120 ns @ 25 MHz.
Regardless of the CPU speed, the DMA controller operates at 10
MHz. Once the DMA and the peripherals are tuned, for example, with a
1:1 interleaving on the Hard Disk, CHIPS/280 continues to deliver
dependable high performance.
***Configurations:...
***Features:...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?
***Info:
The 82C100 is a single chip implementation of most of the system logic
necessary to implement a super XT compatible system with PS/2 Model 30
functionality using either an 8086 or 8088 microprocessor. The 82C100
can be used with either 8 or 16-bit microprocessors. The 82C100
includes features which will enable the PC manufacturer to design a
super PS/2 Model 30/XT compatible system with the highest performance
at 10 MHz zero wait state system with an 8086, the highest
functionality With dual clock and 2.5 MB DRAM (with integrated
Extended Memory System control logic), the lowest power implementation
by utilizing the on-chip power management features and the highest
inte- gration with the lowest component count SMT design.
The 82C100 can be combined with CHIPs‘ 820601 Multifunction Controller
and 82C451 VGA Graphics Controller to provide a high performance, high
integration PS/2 Model 30 type system.
The 82C100 supports most of the peripheral functions on the P8/2 Model
30 planar board: 8284 compatible clock generator with the option of 2
independent oscillators. 8288 compatible bus controller, 8237 comp-
atible DMA controller, 8259 compatible interrupt controller, 8254
compatible timer/counter, 8255 compatible peripheral I/O port, XT Key-
board interface, Parity Generation and Checking for DRAM memory and
memory controller for DRAM and SRAM memory sub-systems.
The 82C100 enables the user to add P8/2 Model 30 superset
functionality on the planar board: dual clock with synchronized
switching between the two clocks, built-in Lotus-Intel-Microsoft (LIM)
EMS support for up to 2.5 Megabytes of DRAM and power management
features for SLEEP mode as well as SUSPEND/RESUME Operations. The
SLEEP and SUSPEND/RESUME features help in preserving the battery life
in laptop portable applications.
The 82C100 Supports a very flexible memory architecture. For systems
with DRAMs, the DRAM controller supports 64K, 256K and 1M DRAMs. These
DRAMs can be organized in four banks of up to a maximum of 2.5 MB on
the planar board. The 2.5 MB memory can be implemented with 2 banks
of 1M x 1 DRAMs, partitioned locally as 640KB of real memory and
1.875MB of EMS memory, For systems which require low operating power
and minimum standby power dissipation, the chips provide the decode
logic which in conjunction with external decoders allows selection of
up to 640KB of static RAM. This option is useful in laptop portable
applications.
The 82C100 is packaged in a 100-pin plastic flatpack.
***Configurations:...
***Features:...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
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*Contaq . . . . . [no datasheets, some info]...
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*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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