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**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91
***Info:
The CS82310 PEAK/DM CHIPSet is a three chip VLSI implementation of the
systems logic required to implement a cache-based 386DX system. This
CHIPSet is designed to offer a 100% PC/AT compatible Integrated
solution. The flexible architecture of the PEAK/DM allows it to be
used in any iAPX386-based system design such as CAD/CAE workstations,
office systems, industrial and financial transaction systems. The
CS82310 PEAK/DM CHIPSet provides a complete cache based 386/AT system
using only 19 components plus memory devices. The CS82310 PEAK/DM
CHIPSet consists of one 82C351 CPU/cache/DRAM controller, one 82C355
data buffer, and one 82C356 peripheral controller. The CHIPSet
supports a local CPU bus, a 32-bit memory bus, and AT buses.
82C351 CPU/Cache/D RAM/Controller
By integrating both the cache and DRAM control functions in one chip,
the 82C351 supports simultaneous activation of cache and DRAM
accesses; minimizing the cache miss penalty. It has hardware support
to allow the user to designate up to four blocks (of variable size
from 4KB to 4MB) of main memory as non-cacheable address space. The
82C351 cache controller supports a direct mapped cache architecture
and cache sizes of 32KB, 64KB, 128KB, or 256KB. Memory write updates
are implemented using a buffered write-through scheme. The 82C351 is
available in a 160-pin PFP package.
82C355 Data Buffer
The 82C355 bus controller contains the data buffers used to interface
the local and system memory buses and a path for the AT data bus. In
addition to having high current bus drive, it also performs
conversions between the different sized data paths and provides parity
generation and checking. The 82C355 is available in a 120-pin PFP
package.
82C356 Peripheral Controller
The 82C356 peripheral controller contains the address buffers used to
interface between the processor address bus (A<23:2>) and the system
address bus (SA<19:0>). It also contains an equivalent 82C206
integrated peripheral controller that incorporates: two 8237 DMA
controllers, two 8259 interrupt controllers, one 8254 timer/counter,
one MC146818 real time clock, and several TTL/SSI interface logic
chips.
***Configurations:...
***Features:...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95
***Info:
The CS4041 is the first product in the GreenCHIPS CHIPSet product
portfolio of Chips and Technologies, Inc. It provides all of the
system logic for implementing a high performance, Energy Star
compliant 486 PC/AT design, while maintaining an extremely competitive
cost structure. The powerful feature set includes the CHIPS "standard"
system blocks and offers a new level of system integration while
addressing the ever evolving requirements that the market place
demands. It is 100% PC/AT compatible and directly supports the 486DX,
486DX2, 486DX4, 486SX and 486 derivatives that support the CPU write
back cache architecture.
The high performance CHIPSet consists of the F84041 Systems Controller
and F84045 GreenCHIPS IPC. The F84041 System Controller is packaged in
a 208-pin PQFP and integrates the major system logic
functions. Included in the F84041 is the CHIPS patented Page
Interleave DRAM controller, high performance cache controller, VL
local bus controller, ISA bus controller, power management module, a
local bus IDE controller and fully compatible 8042 keyboard controller
with PS/2 mouse support. The companion F84045 is packaged in a 100 pin
PQFP and contains the industry standard Integrated Peripheral
Controller (IPC) which includes the DMA controllers, timers, interrupt
controllers and real time clock.
The enhanced feature set of GreenCHIPS DRAM and cache controllers are
perfect for today's High Performance PC/AT designs. The page
interleave DRAM controller offers high performance as well as extreme
flexibility in supporting 486 memory subsystems. The DRAM controller
supports up to eight banks of memory that can be configured with 256K,
1M, 4M or 16M memory devices. Page interleaving, timing modes, memory
mix options, direct drive support and block by block parity support
can be tuned to meet the most optimum requirements for the system
design. In addition, the high performance secondary cache controller
provides options that can be optimized for performance, cost or
both. The direct mapped cache architecture employs internal
comparators with external TAG and data SRAM that can operate in a
write-through or write-back mode. Cache sizes from 64K to 1M are
supported with flexible single bank or dual bank support that allow
flexible timing mode selection based on CPU speed and SRAM speed.
The "Green" in GreenCHIPS comes from the Power management support
integrated in the CHIPSet. The CS4041 provides the perfect level of
power management support for Energy Star compliant desktops. Included
in the power management section is direct support for SMM operation
and clock switching for the popular 486 derivatives. Two event timers,
programmable I/O pins, I/O restart and programmable event detection
provide a wide range of options for power management selection and
customization.
The CS4041 provides new levels of integration in system logic CHIPSets
by providing a local bus IDE interface and keyboard controller. The
robust local bus IDE interface is decoupled from the AT state machine
and does not use a VL local bus load. The interface is versatile
enough to support up to eight IDE drives allowing each drive to have
unique command settings. The result is the best performance for each
drive type allowing significant performance gains over the standard
ISA interface. This is accomplished without any compromise to the
standard VL local bus.
CPUs Supported
oIntel 486 CPUs
oAMD 486 CPUs
oCyrix 486 CPUs
oIBM 486 CPUs
oL1 (CPU) write back cache fully supported
oSMI support (both Intel and Cyrix)
oClock Frequencies:
25MHz, 33MHz, 40MHz, 50MHz
***Configurations:...
***Features:...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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