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**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91
***Info:
The CS82310 PEAK/DM CHIPSet is a three chip VLSI implementation of the
systems logic required to implement a cache-based 386DX system. This
CHIPSet is designed to offer a 100% PC/AT compatible Integrated
solution. The flexible architecture of the PEAK/DM allows it to be
used in any iAPX386-based system design such as CAD/CAE workstations,
office systems, industrial and financial transaction systems. The
CS82310 PEAK/DM CHIPSet provides a complete cache based 386/AT system
using only 19 components plus memory devices. The CS82310 PEAK/DM
CHIPSet consists of one 82C351 CPU/cache/DRAM controller, one 82C355
data buffer, and one 82C356 peripheral controller. The CHIPSet
supports a local CPU bus, a 32-bit memory bus, and AT buses.
82C351 CPU/Cache/D RAM/Controller
By integrating both the cache and DRAM control functions in one chip,
the 82C351 supports simultaneous activation of cache and DRAM
accesses; minimizing the cache miss penalty. It has hardware support
to allow the user to designate up to four blocks (of variable size
from 4KB to 4MB) of main memory as non-cacheable address space. The
82C351 cache controller supports a direct mapped cache architecture
and cache sizes of 32KB, 64KB, 128KB, or 256KB. Memory write updates
are implemented using a buffered write-through scheme. The 82C351 is
available in a 160-pin PFP package.
82C355 Data Buffer
The 82C355 bus controller contains the data buffers used to interface
the local and system memory buses and a path for the AT data bus. In
addition to having high current bus drive, it also performs
conversions between the different sized data paths and provides parity
generation and checking. The 82C355 is available in a 120-pin PFP
package.
82C356 Peripheral Controller
The 82C356 peripheral controller contains the address buffers used to
interface between the processor address bus (A<23:2>) and the system
address bus (SA<19:0>). It also contains an equivalent 82C206
integrated peripheral controller that incorporates: two 8237 DMA
controllers, two 8259 interrupt controllers, one 8254 timer/counter,
one MC146818 real time clock, and several TTL/SSI interface logic
chips.
***Configurations:...
***Features:...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92
***Info:
The WinCHIPS CHIPSet is a three chip set that includes the 64200
Wingine windows Accelerator and the CS4021 PC CHIPSet (two chips).
The WinCHIPS solution is specifically designed to enable systems
companies to offer modular PCs that allow the end user to upgrade both
microprocessor and graphics performance simultaneously. With WinCHIPS
CHIPSet based systems, PC users can easily migrate to more powerful
microprocessors and add or upgrade cache memory subsystems to achieve
maximum computing performance. Simultaneously, the WinCHIPS system
solution provides the ability of Wingine to scale graphics performance
in proportion to increasing microprocessor speed.
The two-chip systems logic elements of WinCHIPS support all 32-bit X86
microprocessors, including i80386DX, Am386, Super38600, Super38605,
i80486SX, i80468DX, and i80486DX2 microprocessors running at up to 50
MHz clock frequencies.
The WinCHIPS solution memory controller technology is designed to
offer the greatest performance for both cache-based and non-cache
based designs. Moreover, the flexible WinCHIPS architecture allows end
users to add a cache subsystem when upgrading to microprocessors
running 25 MHz or faster.
For non-cache 486SX designs, the WinCHIPS' patented page mode and page
interleaved memory controller supports DRAM Burst transfer for systems
running up to 25 MHz. For cache-based Super38605, and 486DX class
systems, WinCHIPS supports 64K to 512K of direct mapped, write back
cache memory. the WinCHIPS cache architecture integrates a write
buffer and zero wait state cache writes for maximum performance.
The WinCHIPS solution is unique in the industry in providing automatic
system wide performance benefits as end users upgrade to faster, more
powerful microprocessors. This is accomplished with the 64200 Wingine
Memory Bus Architecture which can support up to two banks of dual port
VRAM video memory on the microprocessor memory bus. Because the
required video memory control logic is integrated into the WinCHIPS
4021 Bus/DRAM Controller, video memory can be mapped directly into
main memory where it is linearly addressed by the microprocessor.
By allowing the processor to access video memory directly, graphics
functions performed by the processor, such as BIT BLTing, scale with
overall processor power. Hence the bottleneck inherent in today's
local abus and ISA bus graphics subsystems is removed. With the 64200
Wingine, the performance of the display scales correspondingly with
microprocessor power.
WinCHIPS is the industry's first CHIPSet to offer an advanced set of
hardware features designed to specifically support the SuperState
System Management Architecture found on the Super38605 micro-
processors.
***Configurations:...
***Features:...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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