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**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89
***Info:
CHIPS/280 is a 7-device, enhanced CMOS implementation of most of the
system logic necessary to implement personal computers compatible to
IBM PS/2 Model 70/80. CHIPS/280 enables OEMs to offer compatible PS/2
models 70/80, that are more integrated and superior in performance
than IBM's Model 70/80.
CHIPS/280 includes the CS8238 System Logic CHIPSet, the 82C607
Multi-Function Controller with Analog Data Separator and 16550
compatible serial port, and the Enhanced Gate-Level Compatible
82C451/452 VGA chip as indicated in Figures 1a and lb [see data
sheet]. With these 7 VLSI devices, it requires only 59 additional
components plus memory to implement compatible PS/2 Models 70/80
superior to IBM's models.
CHIPS/280 is designed to maximize the performance of the 80386
microprocessor by coupling it to a high performance page/interleaved
memory sub-system. The maximum page size supported by the CHIPS/280
architecture is 16 KBytes when 1 Mbyte DRAMs are used (16 MB of
onboard Memory) and the four way interleaved mode of operation is
selected. When executing within a page, the DRAM memory sub-system can
execute at the same speed as the processor. To the 386, the mem- ory
sub-system appears as a 16 KByte direct mapped cache, using relatively
inexpensive DRAMs. When operating at 16, 20 or 25 MHZ, the average
waitstate incurred is less than 0.7. Additionally, by using Shadow RAM
techniques, the BIOS code can also be executed with near zero wait
states.
In addition to the high performance memory interface, CHIPS/280
supports a fast Matched Memory Cycle reducing the access time from 200
ns to 120 ns at 25 MHz. CHIPS proprietary Fast VGA cycle allows VGA
I/O accesses to be performed within 187.5 ns@ 16 MHz, 150 ns @ 20 MHz,
and 120 ns @ 25 MHz.
Regardless of the CPU speed, the DMA controller operates at 10
MHz. Once the DMA and the peripherals are tuned, for example, with a
1:1 interleaving on the Hard Disk, CHIPS/280 continues to deliver
dependable high performance.
***Configurations:...
***Features:...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89
***Info:
The CS8281 NEATsx CHlPSet, which is composed of four VLSI devices, is
a high-performance, 100%-compatible enhanced implementation of the
control logic used in the IBM PC AT. The flexible architecture of the
NEATsx CHIPSet allows it to be used as the basis for any
386sx-compatible system.
The CS8281 NEATsx CHIPSet provides a complete 386sx PC/AT compatible
system, requiring only 24 logic components plus memory devices.
The CS8281 NEATsx CHIPSet consists of the 82C811 CPU/bus controller,
the 82C812 page/interleave and EMS memory controller, the 82C215
data/address buffer, and the 82C206 integrated peripherals controller
(IPC).
The NEATsx CHIPSet supports a local CPU bus, a 16-bit system memory
bus, and the AT buses as shown in the NEATsx system block diagram [see
datasheet]. The 82C811 provides synchronization and control signals
for all buses. The 82C811 also provides an independent AT bus clock
and allows for dynamic selection between the processor clock and a
user~selectable AT bus clock. Because command delays and wait states
are configured by software, peripheral boards are provided with
maximum flexibility.
The 82C812 page/interleave and EMS memory controller provides an
interleaved memory subsystem design with page mode operation. It sup-
ports up to 8MB of DRAM with combinations of 256Kb and 1Mb DRAMs. The
processor can operate at 16 MHz with 0.7 wait state memory accesses,
using 100 nsec DRAMs. This is possible through a page interleaved
memory scheme. A RAM shadowing feature allows faster execution of
EPROM stored BIOS code by downloading and executing code from RAM. in
a DOS environment memory above 1MB can be used as EMS memory.
The 82C215 data/address buffer provides buffering and latching between
the local CPU address bus and the peripheral address bus. It also
provides buffering between the local CPU data bus and the memory data
bus. Parity bit generation and error detection logic resides in the
82C215.
The 82C206 integrated peripherals controller is an integral part of
the NEATsx CHIPSet. It is described in the 82C206 data book.
System Overview
The CS8281 NEATsx CHIPSet is designed for use in 12-16 MHz 80386 based
systems and provides complete support for the IBM PC AT bus. Four
buses are supported by the CS8281 NEATsx CHIPSet: the CPU local bus (A
and D); the system memory bus (MA and MD); the I/O channel bus (SA and
SD); and the X bus (XA and XD). The system memory bus provides an
interface between the CPU and the DRAMs and EPROMS controlled by the
82C812. The I/O channel bus refers to the bus supporting the
AT-compatible bus adapters which can be either 8- or 16-bit devices.
The X bus is the peripheral bus to which the 82C206 IPC and other
peripherals are attached in an IBM PC AT.
***Configurations:...
***Features:...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
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*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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