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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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*SIS...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98
***Info:
The SiS5591/5592  SiS5595 glueless P5  A.G.P. chipset provides  a high
performance/cost index  Desktop/Mobile solution for  the Intel Pentium
P54C/P55C, AMD K5/K6, and Cyrix M1/M2 A.G.P. system.

The SiS5591/SiS5592  A.G.P./PCI controller integrated  the Host-to-PCI
bridge, the L2 cache  controller, the DRAM controller, the Accelerated
Graphics  Port interface,  and the  PCI IDE  controller. The  L2 cache
controller can  support up to 1  M P.B. SRAM, and  the DRAM controller
can  support EDO/FP/SDRAM memory  up to  768 MB  with optional  ECC or
parity check  function. The  A.G.P. 1.0 compliance  interface supports
both  1X, and  2X speed  mode with  sideband address  capability.  The
built-in fast  PCI IDE  controller supports the  ATA PIO/DMA,  and the
Ultra DMA/33 functionality.

SiS5591  and SiS5592  have some  pin-out switching  to  facilitate the
main-board layout.  SiS5591 pin  assignment is based  on the  ATX form
factor,  and  SiS5592  pin  assignment   is  based  on  the  NLX  form
factor. Beside  the pin-out switching, SiS5591 and  SiS5592 is totally
the same on the internal logic circuit.

The SiS5595 PCI  system I/O integrates the PCI-to-ISA  bridge with the
DDMA,  and  Serial  IRQ  capability,  the ACPI/Legacy  PMU,  the  Data
Acquisition  Interface, the Universal  Serial Bus  host/hub interface,
and the ISA  bus interface which contains the  ISA bus controller, the
DMA controllers,  the interrupt controllers,  and the Timers.  It also
integrates the Keyboard controller, and the Real Time Clock (RTC). The
built-in USB controller,  which is fully compliant to  OHCI (Open Host
Controller  Interface),  provides two  USB  ports  capable of  running
full/low speed USB devices.  The Data Acquisition Interface offers the
ability of monitoring and reporting the environmental condition of the
PC. It could  monitor 4 positive analogue voltage  inputs, 2 Fan speed
inputs, and one temperature input.


***Configurations:...
***Features:...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
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*TI (Texas Instruments)...
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*Unresearched:...
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*Western Digital...
*Winbond...
**W83769          Local Bus IDE Solution                           <94
***Info:
GENERAL DESCRIPTION

The W83769  is a  high-performance, low-cost, highly  integrated logic
design  for IDE hard  disk applications  in PCI  (Peripheral Component
Interconnect)  local  bus systems.  It  provides  a  bridge between  a
standard  IDE  drive  and the  PCI  local  bus.  The W83769  is  fully
compatible  with the  ANSI ATA  3.0 specifications  for IDE  hard disk
operation  and the  PCI SIG  revision 2.0  specifications for  the PCI
local bus  protocol. Packaged in  a 100-pin PQFP, the  W83769 directly
supports the 32-bit PCI bus without requiring any external TTLs.

The W83769  operates at up to 50  MHz and provides a  full 32-bit data
path to the PCI bus. Doubleword read and write operations are provided
via  internal   control  and  conversion  logic.   Write  posting  and
read-ahead  allows CPU  memory  cycles to  run  concurrently with  IDE
cycles and improves the hard disk buffer-to-host transfer rate.

The IDE  drive interface timing  of the W83769 is  completely software
programmable,  including command  active/recovery  timing and  address
setup-hold   timing  for   each  drive.   The  device   supports  Fast
ATA/Enhanced  IDE  mode  3  timing  and IORDY  monitoring  for  better
performance.   The  W83769  directly  supports four  IDE  drives  with
170/1F0   dual   IDE  connectors.   The  IO base   addresses  of   the
primary/secondary  IDE connector  are exchangeable  by  power-on strap
option.

***Versions:...
***Features:...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
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